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authorMark Brown <broonie@opensource.wolfsonmicro.com>2008-09-10 18:58:42 +0100
committerLiam Girdwood <lrg@slimlogic.co.uk>2008-10-13 21:51:52 +0100
commit1d9f9f040035da73d6ee5d2b3b3a25483a980da3 (patch)
treede6decdace491997d40fba0908661fa9ffda5b9c
parent8a62ab4c4eaf5bce4d9cc84b77d6402c4742d9ab (diff)
mfd: Core support for the WM8400 AudioPlus HiFi CODEC and PMU
The WM8400 is a highly integrated audio CODEC and power management unit optimised for use in mobile multimedia applications. This patch adds core support for the WM8400 to the MFD subsystem. Both I2C and SPI access are supported by the hardware but currently only I2C access is implemented. The code is structured to allow SPI support to be slotted in later. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Samuel Ortiz <sameo@openedhand.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat
-rw-r--r--drivers/mfd/Kconfig8
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/wm8400-core.c455
-rw-r--r--include/linux/mfd/wm8400-audio.h1186
-rw-r--r--include/linux/mfd/wm8400-private.h935
5 files changed, 2586 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0dae245c625..a3ddf6581ea 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -87,6 +87,14 @@ config MFD_TC6393XB
help
Support for Toshiba Mobile IO Controller TC6393XB
+config MFD_WM8400
+ tristate "Support Wolfson Microelectronics WM8400"
+ help
+ Support for the Wolfson Microelecronics WM8400 PMIC and audio
+ CODEC. This driver adds provides common support for accessing
+ the device, additional drivers must be enabled in order to use
+ the functionality of the device.
+
endmenu
menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 6abebe36441..1624c7d87a4 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -12,6 +12,8 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o
obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o
obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
+obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
+
obj-$(CONFIG_MFD_CORE) += mfd-core.o
obj-$(CONFIG_MCP) += mcp-core.o
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
new file mode 100644
index 00000000000..6a0cedb5bb8
--- /dev/null
+++ b/drivers/mfd/wm8400-core.c
@@ -0,0 +1,455 @@
+/*
+ * Core driver for WM8400.
+ *
+ * Copyright 2008 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/bug.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/mfd/wm8400-private.h>
+#include <linux/mfd/wm8400-audio.h>
+
+static struct {
+ u16 readable; /* Mask of readable bits */
+ u16 writable; /* Mask of writable bits */
+ u16 vol; /* Mask of volatile bits */
+ int is_codec; /* Register controlled by codec reset */
+ u16 default_val; /* Value on reset */
+} reg_data[] = {
+ { 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
+ { 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
+ { 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
+ { 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
+ { 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */
+ { 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */
+ { 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */
+ { 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */
+ { 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */
+ { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */
+ { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
+ { 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
+ { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
+ { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
+ { 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
+ { 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
+ { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
+ { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
+ { 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
+ { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
+ { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
+ { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
+ { 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
+ { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
+ { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
+ { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
+ { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
+ { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
+ { 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
+ { 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
+ { 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
+ { 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
+ { 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
+ { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
+ { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
+ { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
+ { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
+ { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
+ { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
+ { 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
+ { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
+ { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
+ { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
+ { 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
+ { 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
+ { 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
+ { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
+ { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
+ { 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
+ { 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
+ { 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
+ { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
+ { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
+ { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
+ { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
+ { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
+ { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
+ { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
+ { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
+ { 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
+ { 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
+ { 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
+ { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
+ { 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
+ { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
+ { 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
+ { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
+ { 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
+};
+
+static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
+{
+ int i, ret = 0;
+
+ BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
+
+ /* If there are any volatile reads then read back the entire block */
+ for (i = reg; i < reg + num_regs; i++)
+ if (reg_data[i].vol) {
+ ret = wm8400->read_dev(wm8400->io_data, reg,
+ num_regs, dest);
+ if (ret != 0)
+ return ret;
+ for (i = 0; i < num_regs; i++)
+ dest[i] = be16_to_cpu(dest[i]);
+
+ return 0;
+ }
+
+ /* Otherwise use the cache */
+ memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
+
+ return 0;
+}
+
+static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
+ u16 *src)
+{
+ int ret, i;
+
+ BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
+
+ for (i = 0; i < num_regs; i++) {
+ BUG_ON(!reg_data[reg + i].writable);
+ wm8400->reg_cache[reg + i] = src[i];
+ src[i] = cpu_to_be16(src[i]);
+ }
+
+ /* Do the actual I/O */
+ ret = wm8400->write_dev(wm8400->io_data, reg, num_regs, src);
+ if (ret != 0)
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * wm8400_reg_read - Single register read
+ *
+ * @wm8400: Pointer to wm8400 control structure
+ * @reg: Register to read
+ *
+ * @return Read value
+ */
+u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
+{
+ u16 val;
+
+ mutex_lock(&wm8400->io_lock);
+
+ wm8400_read(wm8400, reg, 1, &val);
+
+ mutex_unlock(&wm8400->io_lock);
+
+ return val;
+}
+EXPORT_SYMBOL_GPL(wm8400_reg_read);
+
+int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
+{
+ int ret;
+
+ mutex_lock(&wm8400->io_lock);
+
+ ret = wm8400_read(wm8400, reg, count, data);
+
+ mutex_unlock(&wm8400->io_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(wm8400_block_read);
+
+/**
+ * wm8400_set_bits - Bitmask write
+ *
+ * @wm8400: Pointer to wm8400 control structure
+ * @reg: Register to access
+ * @mask: Mask of bits to change
+ * @val: Value to set for masked bits
+ */
+int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
+{
+ u16 tmp;
+ int ret;
+
+ mutex_lock(&wm8400->io_lock);
+
+ ret = wm8400_read(wm8400, reg, 1, &tmp);
+ tmp = (tmp & ~mask) | val;
+ if (ret == 0)
+ ret = wm8400_write(wm8400, reg, 1, &tmp);
+
+ mutex_unlock(&wm8400->io_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(wm8400_set_bits);
+
+/**
+ * wm8400_reset_codec_reg_cache - Reset cached codec registers to
+ * their default values.
+ */
+void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
+{
+ int i;
+
+ mutex_lock(&wm8400->io_lock);
+
+ /* Reset all codec registers to their initial value */
+ for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
+ if (reg_data[i].is_codec)
+ wm8400->reg_cache[i] = reg_data[i].default_val;
+
+ mutex_unlock(&wm8400->io_lock);
+}
+EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
+
+/*
+ * wm8400_init - Generic initialisation
+ *
+ * The WM8400 can be configured as either an I2C or SPI device. Probe
+ * functions for each bus set up the accessors then call into this to
+ * set up the device itself.
+ */
+static int wm8400_init(struct wm8400 *wm8400,
+ struct wm8400_platform_data *pdata)
+{
+ u16 reg;
+ int ret, i;
+
+ mutex_init(&wm8400->io_lock);
+
+ wm8400->dev->driver_data = wm8400;
+
+ /* Check that this is actually a WM8400 */
+ ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg);
+ if (ret != 0) {
+ dev_err(wm8400->dev, "Chip ID register read failed\n");
+ return -EIO;
+ }
+ if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) {
+ dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
+ be16_to_cpu(reg));
+ return -ENODEV;
+ }
+
+ /* We don't know what state the hardware is in and since this
+ * is a PMIC we can't reset it safely so initialise the register
+ * cache from the hardware.
+ */
+ ret = wm8400->read_dev(wm8400->io_data, 0,
+ ARRAY_SIZE(wm8400->reg_cache),
+ wm8400->reg_cache);
+ if (ret != 0) {
+ dev_err(wm8400->dev, "Register cache read failed\n");
+ return -EIO;
+ }
+ for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
+ wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
+
+ /* If the codec is in reset use hard coded values */
+ if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
+ for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
+ if (reg_data[i].is_codec)
+ wm8400->reg_cache[i] = reg_data[i].default_val;
+
+ ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
+ if (ret != 0) {
+ dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
+ return ret;
+ }
+ reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
+ dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
+
+ if (pdata && pdata->platform_init) {
+ ret = pdata->platform_init(wm8400->dev);
+ if (ret != 0)
+ dev_err(wm8400->dev, "Platform init failed: %d\n",
+ ret);
+ } else
+ dev_warn(wm8400->dev, "No platform initialisation supplied\n");
+
+ return ret;
+}
+
+static void wm8400_release(struct wm8400 *wm8400)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(wm8400->regulators); i++)
+ if (wm8400->regulators[i].name)
+ platform_device_unregister(&wm8400->regulators[i]);
+}
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest)
+{
+ struct i2c_client *i2c = io_data;
+ struct i2c_msg xfer[2];
+ int ret;
+
+ /* Write register */
+ xfer[0].addr = i2c->addr;
+ xfer[0].flags = 0;
+ xfer[0].len = 1;
+ xfer[0].buf = &reg;
+
+ /* Read data */
+ xfer[1].addr = i2c->addr;
+ xfer[1].flags = I2C_M_RD;
+ xfer[1].len = count * sizeof(u16);
+ xfer[1].buf = (u8 *)dest;
+
+ ret = i2c_transfer(i2c->adapter, xfer, 2);
+ if (ret == 2)
+ ret = 0;
+ else if (ret >= 0)
+ ret = -EIO;
+
+ return ret;
+}
+
+static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src)
+{
+ struct i2c_client *i2c = io_data;
+ u8 *msg;
+ int ret;
+
+ /* We add 1 byte for device register - ideally I2C would gather. */
+ msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL);
+ if (msg == NULL)
+ return -ENOMEM;
+
+ msg[0] = reg;
+ memcpy(&msg[1], src, count * sizeof(u16));
+
+ ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1);
+
+ if (ret == (count * 2) + 1)
+ ret = 0;
+ else if (ret >= 0)
+ ret = -EIO;
+
+ kfree(msg);
+
+ return ret;
+}
+
+static int wm8400_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ struct wm8400 *wm8400;
+ int ret;
+
+ wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL);
+ if (wm8400 == NULL) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ wm8400->io_data = i2c;
+ wm8400->read_dev = wm8400_i2c_read;
+ wm8400->write_dev = wm8400_i2c_write;
+ wm8400->dev = &i2c->dev;
+ i2c_set_clientdata(i2c, wm8400);
+
+ ret = wm8400_init(wm8400, i2c->dev.platform_data);
+ if (ret != 0)
+ goto struct_err;
+
+ return 0;
+
+struct_err:
+ i2c_set_clientdata(i2c, NULL);
+ kfree(wm8400);
+err:
+ return ret;
+}
+
+static int wm8400_i2c_remove(struct i2c_client *i2c)
+{
+ struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
+
+ wm8400_release(wm8400);
+ i2c_set_clientdata(i2c, NULL);
+ kfree(wm8400);
+
+ return 0;
+}
+
+static const struct i2c_device_id wm8400_i2c_id[] = {
+ { "wm8400", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
+
+static struct i2c_driver wm8400_i2c_driver = {
+ .driver = {
+ .name = "WM8400",
+ .owner = THIS_MODULE,
+ },
+ .probe = wm8400_i2c_probe,
+ .remove = wm8400_i2c_remove,
+ .id_table = wm8400_i2c_id,
+};
+#endif
+
+static int __init wm8400_module_init(void)
+{
+ int ret = -ENODEV;
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+ ret = i2c_add_driver(&wm8400_i2c_driver);
+ if (ret != 0)
+ pr_err("Failed to register I2C driver: %d\n", ret);
+#endif
+
+ return ret;
+}
+module_init(wm8400_module_init);
+
+static void __exit wm8400_module_exit(void)
+{
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+ i2c_del_driver(&wm8400_i2c_driver);
+#endif
+}
+module_exit(wm8400_module_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
diff --git a/include/linux/mfd/wm8400-audio.h b/include/linux/mfd/wm8400-audio.h
new file mode 100644
index 00000000000..b6640e01804
--- /dev/null
+++ b/include/linux/mfd/wm8400-audio.h
@@ -0,0 +1,1186 @@
+/*
+ * wm8400 private definitions for audio
+ *
+ * Copyright 2008 Wolfson Microelectronics plc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __LINUX_MFD_WM8400_AUDIO_H
+#define __LINUX_MFD_WM8400_AUDIO_H
+
+#include <linux/mfd/wm8400-audio.h>
+
+/*
+ * R2 (0x02) - Power Management (1)
+ */
+#define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
+#define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
+#define WM8400_CODEC_ENA_SHIFT 15 /* CODEC_ENA */
+#define WM8400_CODEC_ENA_WIDTH 1 /* CODEC_ENA */
+#define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
+#define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
+#define WM8400_SYSCLK_ENA_SHIFT 14 /* SYSCLK_ENA */
+#define WM8400_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
+#define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
+#define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
+#define WM8400_SPK_MIX_ENA_SHIFT 13 /* SPK_MIX_ENA */
+#define WM8400_SPK_MIX_ENA_WIDTH 1 /* SPK_MIX_ENA */
+#define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
+#define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
+#define WM8400_SPK_ENA_SHIFT 12 /* SPK_ENA */
+#define WM8400_SPK_ENA_WIDTH 1 /* SPK_ENA */
+#define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
+#define WM8400_OUT3_ENA_MASK 0x0800 /* OUT3_ENA */
+#define WM8400_OUT3_ENA_SHIFT 11 /* OUT3_ENA */
+#define WM8400_OUT3_ENA_WIDTH 1 /* OUT3_ENA */
+#define WM8400_OUT4_ENA 0x0400 /* OUT4_ENA */
+#define WM8400_OUT4_ENA_MASK 0x0400 /* OUT4_ENA */
+#define WM8400_OUT4_ENA_SHIFT 10 /* OUT4_ENA */
+#define WM8400_OUT4_ENA_WIDTH 1 /* OUT4_ENA */
+#define WM8400_LOUT_ENA 0x0200 /* LOUT_ENA */
+#define WM8400_LOUT_ENA_MASK 0x0200 /* LOUT_ENA */
+#define WM8400_LOUT_ENA_SHIFT 9 /* LOUT_ENA */
+#define WM8400_LOUT_ENA_WIDTH 1 /* LOUT_ENA */
+#define WM8400_ROUT_ENA 0x0100 /* ROUT_ENA */
+#define WM8400_ROUT_ENA_MASK 0x0100 /* ROUT_ENA */
+#define WM8400_ROUT_ENA_SHIFT 8 /* ROUT_ENA */
+#define WM8400_ROUT_ENA_WIDTH 1 /* ROUT_ENA */
+#define WM8400_MIC1BIAS_ENA 0x0010 /* MIC1BIAS_ENA */
+#define WM8400_MIC1BIAS_ENA_MASK 0x0010 /* MIC1BIAS_ENA */
+#define WM8400_MIC1BIAS_ENA_SHIFT 4 /* MIC1BIAS_ENA */
+#define WM8400_MIC1BIAS_ENA_WIDTH 1 /* MIC1BIAS_ENA */
+#define WM8400_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
+#define WM8400_VMID_MODE_SHIFT 1 /* VMID_MODE - [2:1] */
+#define WM8400_VMID_MODE_WIDTH 2 /* VMID_MODE - [2:1] */
+#define WM8400_VREF_ENA 0x0001 /* VREF_ENA */
+#define WM8400_VREF_ENA_MASK 0x0001 /* VREF_ENA */
+#define WM8400_VREF_ENA_SHIFT 0 /* VREF_ENA */
+#define WM8400_VREF_ENA_WIDTH 1 /* VREF_ENA */
+
+/*
+ * R3 (0x03) - Power Management (2)
+ */
+#define WM8400_FLL_ENA 0x8000 /* FLL_ENA */
+#define WM8400_FLL_ENA_MASK 0x8000 /* FLL_ENA */
+#define WM8400_FLL_ENA_SHIFT 15 /* FLL_ENA */
+#define WM8400_FLL_ENA_WIDTH 1 /* FLL_ENA */
+#define WM8400_TSHUT_ENA 0x4000 /* TSHUT_ENA */
+#define WM8400_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
+#define WM8400_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
+#define WM8400_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
+#define WM8400_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
+#define WM8400_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
+#define WM8400_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
+#define WM8400_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
+#define WM8400_OPCLK_ENA 0x0800 /* OPCLK_ENA */
+#define WM8400_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
+#define WM8400_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
+#define WM8400_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
+#define WM8400_AINL_ENA 0x0200 /* AINL_ENA */
+#define WM8400_AINL_ENA_MASK 0x0200 /* AINL_ENA */
+#define WM8400_AINL_ENA_SHIFT 9 /* AINL_ENA */
+#define WM8400_AINL_ENA_WIDTH 1 /* AINL_ENA */
+#define WM8400_AINR_ENA 0x0100 /* AINR_ENA */
+#define WM8400_AINR_ENA_MASK 0x0100 /* AINR_ENA */
+#define WM8400_AINR_ENA_SHIFT 8 /* AINR_ENA */
+#define WM8400_AINR_ENA_WIDTH 1 /* AINR_ENA */
+#define WM8400_LIN34_ENA 0x0080 /* LIN34_ENA */
+#define WM8400_LIN34_ENA_MASK 0x0080 /* LIN34_ENA */
+#define WM8400_LIN34_ENA_SHIFT 7 /* LIN34_ENA */
+#define WM8400_LIN34_ENA_WIDTH 1 /* LIN34_ENA */
+#define WM8400_LIN12_ENA 0x0040 /* LIN12_ENA */
+#define WM8400_LIN12_ENA_MASK 0x0040 /* LIN12_ENA */
+#define WM8400_LIN12_ENA_SHIFT 6 /* LIN12_ENA */
+#define WM8400_LIN12_ENA_WIDTH 1 /* LIN12_ENA */
+#define WM8400_RIN34_ENA 0x0020 /* RIN34_ENA */
+#define WM8400_RIN34_ENA_MASK 0x0020 /* RIN34_ENA */
+#define WM8400_RIN34_ENA_SHIFT 5 /* RIN34_ENA */
+#define WM8400_RIN34_ENA_WIDTH 1 /* RIN34_ENA */
+#define WM8400_RIN12_ENA 0x0010 /* RIN12_ENA */
+#define WM8400_RIN12_ENA_MASK 0x0010 /* RIN12_ENA */
+#define WM8400_RIN12_ENA_SHIFT 4 /* RIN12_ENA */
+#define WM8400_RIN12_ENA_WIDTH 1 /* RIN12_ENA */
+#define WM8400_ADCL_ENA 0x0002 /* ADCL_ENA */
+#define WM8400_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
+#define WM8400_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
+#define WM8400_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
+#define WM8400_ADCR_ENA 0x0001 /* ADCR_ENA */
+#define WM8400_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
+#define WM8400_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
+#define WM8400_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
+
+/*
+ * R4 (0x04) - Power Management (3)
+ */
+#define WM8400_LON_ENA 0x2000 /* LON_ENA */
+#define WM8400_LON_ENA_MASK 0x2000 /* LON_ENA */
+#define WM8400_LON_ENA_SHIFT 13 /* LON_ENA */
+#define WM8400_LON_ENA_WIDTH 1 /* LON_ENA */
+#define WM8400_LOP_ENA 0x1000 /* LOP_ENA */
+#define WM8400_LOP_ENA_MASK 0x1000 /* LOP_ENA */
+#define WM8400_LOP_ENA_SHIFT 12 /* LOP_ENA */
+#define WM8400_LOP_ENA_WIDTH 1 /* LOP_ENA */
+#define WM8400_RON_ENA 0x0800 /* RON_ENA */
+#define WM8400_RON_ENA_MASK 0x0800 /* RON_ENA */
+#define WM8400_RON_ENA_SHIFT 11 /* RON_ENA */
+#define WM8400_RON_ENA_WIDTH 1 /* RON_ENA */
+#define WM8400_ROP_ENA 0x0400 /* ROP_ENA */
+#define WM8400_ROP_ENA_MASK 0x0400 /* ROP_ENA */
+#define WM8400_ROP_ENA_SHIFT 10 /* ROP_ENA */
+#define WM8400_ROP_ENA_WIDTH 1 /* ROP_ENA */
+#define WM8400_LOPGA_ENA 0x0080 /* LOPGA_ENA */
+#define WM8400_LOPGA_ENA_MASK 0x0080 /* LOPGA_ENA */
+#define WM8400_LOPGA_ENA_SHIFT 7 /* LOPGA_ENA */
+#define WM8400_LOPGA_ENA_WIDTH 1 /* LOPGA_ENA */
+#define WM8400_ROPGA_ENA 0x0040 /* ROPGA_ENA */
+#define WM8400_ROPGA_ENA_MASK 0x0040 /* ROPGA_ENA */
+#define WM8400_ROPGA_ENA_SHIFT 6 /* ROPGA_ENA */
+#define WM8400_ROPGA_ENA_WIDTH 1 /* ROPGA_ENA */
+#define WM8400_LOMIX_ENA 0x0020 /* LOMIX_ENA */
+#define WM8400_LOMIX_ENA_MASK 0x0020 /* LOMIX_ENA */
+#define WM8400_LOMIX_ENA_SHIFT 5 /* LOMIX_ENA */
+#define WM8400_LOMIX_ENA_WIDTH 1 /* LOMIX_ENA */
+#define WM8400_ROMIX_ENA 0x0010 /* ROMIX_ENA */
+#define WM8400_ROMIX_ENA_MASK 0x0010 /* ROMIX_ENA */
+#define WM8400_ROMIX_ENA_SHIFT 4 /* ROMIX_ENA */
+#define WM8400_ROMIX_ENA_WIDTH 1 /* ROMIX_ENA */
+#define WM8400_DACL_ENA 0x0002 /* DACL_ENA */
+#define WM8400_DACL_ENA_MASK 0x0002 /* DACL_ENA */
+#define WM8400_DACL_ENA_SHIFT 1 /* DACL_ENA */
+#define WM8400_DACL_ENA_WIDTH 1 /* DACL_ENA */
+#define WM8400_DACR_ENA 0x0001 /* DACR_ENA */
+#define WM8400_DACR_ENA_MASK 0x0001 /* DACR_ENA */
+#define WM8400_DACR_ENA_SHIFT 0 /* DACR_ENA */
+#define WM8400_DACR_ENA_WIDTH 1 /* DACR_ENA */
+
+/*
+ * R5 (0x05) - Audio Interface (1)
+ */
+#define WM8400_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
+#define WM8400_AIFADCL_SRC_MASK 0x8000 /* AIFADCL_SRC */
+#define WM8400_AIFADCL_SRC_SHIFT 15 /* AIFADCL_SRC */
+#define WM8400_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */
+#define WM8400_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
+#define WM8400_AIFADCR_SRC_MASK 0x4000 /* AIFADCR_SRC */
+#define WM8400_AIFADCR_SRC_SHIFT 14 /* AIFADCR_SRC */
+#define WM8400_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */
+#define WM8400_AIFADC_TDM 0x2000 /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_MASK 0x2000 /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_SHIFT 13 /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
+#define WM8400_AIFADC_TDM_CHAN_MASK 0x1000 /* AIFADC_TDM_CHAN */
+#define WM8400_AIFADC_TDM_CHAN_SHIFT 12 /* AIFADC_TDM_CHAN */
+#define WM8400_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */
+#define WM8400_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
+#define WM8400_AIF_BCLK_INV_MASK 0x0100 /* AIF_BCLK_INV */
+#define WM8400_AIF_BCLK_INV_SHIFT 8 /* AIF_BCLK_INV */
+#define WM8400_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
+#define WM8400_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
+#define WM8400_AIF_LRCLK_INV_MASK 0x0080 /* AIF_LRCLK_INV */
+#define WM8400_AIF_LRCLK_INV_SHIFT 7 /* AIF_LRCLK_INV */
+#define WM8400_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
+#define WM8400_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
+#define WM8400_AIF_WL_SHIFT 5 /* AIF_WL - [6:5] */
+#define WM8400_AIF_WL_WIDTH 2 /* AIF_WL - [6:5] */
+#define WM8400_AIF_WL_16BITS (0 << 5)
+#define WM8400_AIF_WL_20BITS (1 << 5)
+#define WM8400_AIF_WL_24BITS (2 << 5)
+#define WM8400_AIF_WL_32BITS (3 << 5)
+#define WM8400_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
+#define WM8400_AIF_FMT_SHIFT 3 /* AIF_FMT - [4:3] */
+#define WM8400_AIF_FMT_WIDTH 2 /* AIF_FMT - [4:3] */
+#define WM8400_AIF_FMT_RIGHTJ (0 << 3)
+#define WM8400_AIF_FMT_LEFTJ (1 << 3)
+#define WM8400_AIF_FMT_I2S (2 << 3)
+#define WM8400_AIF_FMT_DSP (3 << 3)
+
+/*
+ * R6 (0x06) - Audio Interface (2)
+ */
+#define WM8400_DACL_SRC 0x8000 /* DACL_SRC */
+#define WM8400_DACL_SRC_MASK 0x8000 /* DACL_SRC */
+#define WM8400_DACL_SRC_SHIFT 15 /* DACL_SRC */
+#define WM8400_DACL_SRC_WIDTH 1 /* DACL_SRC */
+#define WM8400_DACR_SRC 0x4000 /* DACR_SRC */
+#define WM8400_DACR_SRC_MASK 0x4000 /* DACR_SRC */
+#define WM8400_DACR_SRC_SHIFT 14 /* DACR_SRC */
+#define WM8400_DACR_SRC_WIDTH 1 /* DACR_SRC */
+#define WM8400_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
+#define WM8400_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */
+#define WM8400_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */
+#define WM8400_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */
+#define WM8400_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */
+#define WM8400_DAC_BOOST_SHIFT 10 /* DAC_BOOST - [11:10] */
+#define WM8400_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [11:10] */
+#define WM8400_DAC_COMP 0x0010 /* DAC_COMP */
+#define WM8400_DAC_COMP_MASK 0x0010 /* DAC_COMP */
+#define WM8400_DAC_COMP_SHIFT 4 /* DAC_COMP */
+#define WM8400_DAC_COMP_WIDTH 1 /* DAC_COMP */
+#define WM8400_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
+#define WM8400_DAC_COMPMODE_MASK 0x0008 /* DAC_COMPMODE */
+#define WM8400_DAC_COMPMODE_SHIFT 3 /* DAC_COMPMODE */
+#define WM8400_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
+#define WM8400_ADC_COMP 0x0004 /* ADC_COMP */
+#define WM8400_ADC_COMP_MASK 0x0004 /* ADC_COMP */
+#define WM8400_ADC_COMP_SHIFT 2 /* ADC_COMP */
+#define WM8400_ADC_COMP_WIDTH 1 /* ADC_COMP */
+#define WM8400_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
+#define WM8400_ADC_COMPMODE_MASK 0x0002 /* ADC_COMPMODE */
+#define WM8400_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */
+#define WM8400_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */
+#define WM8400_LOOPBACK 0x0001 /* LOOPBACK */
+#define WM8400_LOOPBACK_MASK 0x0001 /* LOOPBACK */
+#define WM8400_LOOPBACK_SHIFT 0 /* LOOPBACK */
+#define WM8400_LOOPBACK_WIDTH 1 /* LOOPBACK */
+
+/*
+ * R7 (0x07) - Clocking (1)
+ */
+#define WM8400_TOCLK_RATE 0x8000 /* TOCLK_RATE */
+#define WM8400_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */
+#define WM8400_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */
+#define WM8400_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */
+#define WM8400_TOCLK_ENA 0x4000 /* TOCLK_ENA */
+#define WM8400_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */
+#define WM8400_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */
+#define WM8400_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
+#define WM8400_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
+#define WM8400_OPCLKDIV_SHIFT 9 /* OPCLKDIV - [12:9] */
+#define WM8400_OPCLKDIV_WIDTH 4 /* OPCLKDIV - [12:9] */
+#define WM8400_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
+#define WM8400_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */
+#define WM8400_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */
+#define WM8400_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
+#define WM8400_BCLK_DIV_SHIFT 1 /* BCLK_DIV - [4:1] */
+#define WM8400_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [4:1] */
+
+/*
+ * R8 (0x08) - Clocking (2)
+ */
+#define WM8400_MCLK_SRC 0x8000 /* MCLK_SRC */
+#define WM8400_MCLK_SRC_MASK 0x8000 /* MCLK_SRC */
+#define WM8400_MCLK_SRC_SHIFT 15 /* MCLK_SRC */
+#define WM8400_MCLK_SRC_WIDTH 1 /* MCLK_SRC */
+#define WM8400_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
+#define WM8400_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */
+#define WM8400_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */
+#define WM8400_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
+#define WM8400_CLK_FORCE 0x2000 /* CLK_FORCE */
+#define WM8400_CLK_FORCE_MASK 0x2000 /* CLK_FORCE */
+#define WM8400_CLK_FORCE_SHIFT 13 /* CLK_FORCE */
+#define WM8400_CLK_FORCE_WIDTH 1 /* CLK_FORCE */
+#define WM8400_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
+#define WM8400_MCLK_DIV_SHIFT 11 /* MCLK_DIV - [12:11] */
+#define WM8400_MCLK_DIV_WIDTH 2 /* MCLK_DIV - [12:11] */
+#define WM8400_MCLK_INV 0x0400 /* MCLK_INV */
+#define WM8400_MCLK_INV_MASK 0x0400 /* MCLK_INV */
+#define WM8400_MCLK_INV_SHIFT 10 /* MCLK_INV */
+#define WM8400_MCLK_INV_WIDTH 1 /* MCLK_INV */
+#define WM8400_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */
+#define WM8400_ADC_CLKDIV_SHIFT 5 /* ADC_CLKDIV - [7:5] */
+#define WM8400_ADC_CLKDIV_WIDTH 3 /* ADC_CLKDIV - [7:5] */
+#define WM8400_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
+#define WM8400_DAC_CLKDIV_SHIFT 2 /* DAC_CLKDIV - [4:2] */
+#define WM8400_DAC_CLKDIV_WIDTH 3 /* DAC_CLKDIV - [4:2] */
+
+/*
+ * R9 (0x09) - Audio Interface (3)
+ */
+#define WM8400_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR1_MASK 0x8000 /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR1_SHIFT 15 /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR1_WIDTH 1 /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
+#define WM8400_AIF_MSTR2_MASK 0x4000 /* AIF_MSTR2 */
+#define WM8400_AIF_MSTR2_SHIFT 14 /* AIF_MSTR2 */
+#define WM8400_AIF_MSTR2_WIDTH 1 /* AIF_MSTR2 */
+#define WM8400_AIF_SEL 0x2000 /* AIF_SEL */
+#define WM8400_AIF_SEL_MASK 0x2000 /* AIF_SEL */
+#define WM8400_AIF_SEL_SHIFT 13 /* AIF_SEL */
+#define WM8400_AIF_SEL_WIDTH 1 /* AIF_SEL */
+#define WM8400_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
+#define WM8400_ADCLRC_DIR_MASK 0x0800 /* ADCLRC_DIR */
+#define WM8400_ADCLRC_DIR_SHIFT 11 /* ADCLRC_DIR */
+#define WM8400_ADCLRC_DIR_WIDTH 1 /* ADCLRC_DIR */
+#define WM8400_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */
+#define WM8400_ADCLRC_RATE_SHIFT 0 /* ADCLRC_RATE - [10:0] */
+#define WM8400_ADCLRC_RATE_WIDTH 11 /* ADCLRC_RATE - [10:0] */
+
+/*
+ * R10 (0x0A) - Audio Interface (4)
+ */
+#define WM8400_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
+#define WM8400_ALRCGPIO1_MASK 0x8000 /* ALRCGPIO1 */
+#define WM8400_ALRCGPIO1_SHIFT 15 /* ALRCGPIO1 */
+#define WM8400_ALRCGPIO1_WIDTH 1 /* ALRCGPIO1 */
+#define WM8400_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
+#define WM8400_ALRCBGPIO6_MASK 0x4000 /* ALRCBGPIO6 */
+#define WM8400_ALRCBGPIO6_SHIFT 14 /* ALRCBGPIO6 */
+#define WM8400_ALRCBGPIO6_WIDTH 1 /* ALRCBGPIO6 */
+#define WM8400_AIF_TRIS 0x2000 /* AIF_TRIS */
+#define WM8400_AIF_TRIS_MASK 0x2000 /* AIF_TRIS */
+#define WM8400_AIF_TRIS_SHIFT 13 /* AIF_TRIS */
+#define WM8400_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
+#define WM8400_DACLRC_DIR 0x0800 /* DACLRC_DIR */
+#define WM8400_DACLRC_DIR_MASK 0x0800 /* DACLRC_DIR */
+#define WM8400_DACLRC_DIR_SHIFT 11 /* DACLRC_DIR */
+#define WM8400_DACLRC_DIR_WIDTH 1 /* DACLRC_DIR */
+#define WM8400_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */
+#define WM8400_DACLRC_RATE_SHIFT 0 /* DACLRC_RATE - [10:0] */
+#define WM8400_DACLRC_RATE_WIDTH 11 /* DACLRC_RATE - [10:0] */
+
+/*
+ * R11 (0x0B) - DAC CTRL
+ */
+#define WM8400_DAC_SDMCLK_RATE 0x2000 /* DAC_SDMCLK_RATE */
+#define WM8400_DAC_SDMCLK_RATE_MASK 0x2000 /* DAC_SDMCLK_RATE */
+#define WM8400_DAC_SDMCLK_RATE_SHIFT 13 /* DAC_SDMCLK_RATE */
+#define WM8400_DAC_SDMCLK_RATE_WIDTH 1 /* DAC_SDMCLK_RATE */
+#define WM8400_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
+#define WM8400_AIF_LRCLKRATE_MASK 0x0400 /* AIF_LRCLKRATE */
+#define WM8400_AIF_LRCLKRATE_SHIFT 10 /* AIF_LRCLKRATE */
+#define WM8400_AIF_LRCLKRATE_WIDTH 1 /* AIF_LRCLKRATE */
+#defin