diff options
| author | Takashi Iwai <tiwai@suse.de> | 2011-04-21 15:27:58 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2011-04-21 15:27:58 +0200 |
| commit | 885f42e1f466c36e3663d912a831e940f01a112b (patch) | |
| tree | 8660217c1070b8d16f61db7750364391de917443 | |
| parent | d2edeb7c6f1dada8ca7d5c23e42d604e92ae0c76 (diff) | |
ALSA: hda - Enable sync_write for AMD chipset with IDT 92HD8x codecs
The AMD chipset seems unstable in the normal operation mode, and it
seems requring more sensible access for each verb. Enabling sync_write
mode and allowing bus-reset is a sort of workaround for these chipset
stability issues.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
| -rw-r--r-- | sound/pci/hda/patch_sigmatel.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 05fcd60cc46..c391bfb95e0 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -5446,6 +5446,13 @@ static int patch_stac92hd83xxx(struct hda_codec *codec) spec->multiout.dac_nids = spec->dac_nids; spec->init = stac92hd83xxx_core_init; + if (codec->bus->pci && codec->bus->pci->vendor == PCI_VENDOR_ID_AMD) { + snd_printk(KERN_INFO "idt92hd83xxx: " + "Enable sync_write for AMD chipset\n"); + codec->bus->sync_write = 1; + codec->bus->allow_bus_reset = 1; + } + spec->board_config = snd_hda_check_board_config(codec, STAC_92HD83XXX_MODELS, stac92hd83xxx_models, |