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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-01-19 15:51:11 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 17:50:15 +0000
commit44dc9d027f1cb56625b1011d8725d2ab614c04e6 (patch)
tree582577d2bae2c613d63147a935688186c900b624
parent8ad8ff6548f1c0bcbeaa02f274b3927c5015a921 (diff)
[ARM] omap: convert OMAP3 to use clkdev
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-omap2/clock34xx.c268
-rw-r--r--arch/arm/mach-omap2/clock34xx.h513
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/include/mach/clock.h5
4 files changed, 331 insertions, 456 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 52698fb4fd0..2c22750016c 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,6 +30,7 @@
#include <mach/clock.h>
#include <mach/sram.h>
#include <asm/div64.h>
+#include <asm/clkdev.h>
#include "memory.h"
#include "clock.h"
@@ -42,6 +43,240 @@ static const struct clkops clkops_noncore_dpll_ops;
#include "clock34xx.h"
+struct omap_clk {
+ u32 cpu;
+ struct clk_lookup lk;
+};
+
+#define CLK(dev, con, ck, cp) \
+ { \
+ .cpu = cp, \
+ .lk = { \
+ .dev_id = dev, \
+ .con_id = con, \
+ .clk = ck, \
+ }, \
+ }
+
+#define CK_343X (1 << 0)
+#define CK_3430ES1 (1 << 1)
+#define CK_3430ES2 (1 << 2)
+
+static struct omap_clk omap34xx_clks[] = {
+ CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
+ CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
+ CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
+ CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
+ CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
+ CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
+ CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
+ CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
+ CLK(NULL, "sys_ck", &sys_ck, CK_343X),
+ CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
+ CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
+ CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
+ CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
+ CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
+ CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
+ CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
+ CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
+ CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
+ CLK(NULL, "core_ck", &core_ck, CK_343X),
+ CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
+ CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
+ CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
+ CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
+ CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
+ CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
+ CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
+ CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
+ CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
+ CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
+ CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
+ CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
+ CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
+ CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
+ CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
+ CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
+ CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
+ CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
+ CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
+ CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
+ CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
+ CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
+ CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
+ CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
+ CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
+ CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
+ CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
+ CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
+ CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
+ CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
+ CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
+ CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
+ CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
+ CLK(NULL, "arm_fck", &arm_fck, CK_343X),
+ CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+ CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
+ CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
+ CLK(NULL, "l3_ick", &l3_ick, CK_343X),
+ CLK(NULL, "l4_ick", &l4_ick, CK_343X),
+ CLK(NULL, "rm_ick", &rm_ick, CK_343X),
+ CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
+ CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
+ CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
+ CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
+ CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
+ CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
+ CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
+ CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
+ CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
+ CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
+ CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
+ CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
+ CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
+ CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
+ CLK("mmci-omap-hs.2", "mmchs_fck", &mmchs3_fck, CK_3430ES2),
+ CLK("mmci-omap-hs.1", "mmchs_fck", &mmchs2_fck, CK_343X),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
+ CLK("mmci-omap-hs.0", "mmchs_fck", &mmchs1_fck, CK_343X),
+ CLK("i2c_omap.3", "i2c_fck", &i2c3_fck, CK_343X),
+ CLK("i2c_omap.2", "i2c_fck", &i2c2_fck, CK_343X),
+ CLK("i2c_omap.1", "i2c_fck", &i2c1_fck, CK_343X),
+ CLK("omap-mcbsp.5", "mcbsp_fck", &mcbsp5_fck, CK_343X),
+ CLK("omap-mcbsp.1", "mcbsp_fck", &mcbsp1_fck, CK_343X),
+ CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
+ CLK("omap2_mcspi.4", "mcspi_fck", &mcspi4_fck, CK_343X),
+ CLK("omap2_mcspi.3", "mcspi_fck", &mcspi3_fck, CK_343X),
+ CLK("omap2_mcspi.2", "mcspi_fck", &mcspi2_fck, CK_343X),
+ CLK("omap2_mcspi.1", "mcspi_fck", &mcspi1_fck, CK_343X),
+ CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
+ CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
+ CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
+ CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
+ CLK(NULL, "hdq_fck", &hdq_fck, CK_343X),
+ CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
+ CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
+ CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
+ CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
+ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
+ CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
+ CLK(NULL, "pka_ick", &pka_ick, CK_343X),
+ CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
+ CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
+ CLK("mmci-omap-hs.2", "mmchs_ick", &mmchs3_ick, CK_3430ES2),
+ CLK(NULL, "icr_ick", &icr_ick, CK_343X),
+ CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
+ CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
+ CLK(NULL, "des2_ick", &des2_ick, CK_343X),
+ CLK("mmci-omap-hs.1", "mmchs_ick", &mmchs2_ick, CK_343X),
+ CLK("mmci-omap-hs.0", "mmchs_ick", &mmchs1_ick, CK_343X),
+ CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
+ CLK(NULL, "hdq_ick", &hdq_ick, CK_343X),
+ CLK("omap2_mcspi.4", "mcspi_ick", &mcspi4_ick, CK_343X),
+ CLK("omap2_mcspi.3", "mcspi_ick", &mcspi3_ick, CK_343X),
+ CLK("omap2_mcspi.2", "mcspi_ick", &mcspi2_ick, CK_343X),
+ CLK("omap2_mcspi.1", "mcspi_ick", &mcspi1_ick, CK_343X),
+ CLK("i2c_omap.3", "i2c_ick", &i2c3_ick, CK_343X),
+ CLK("i2c_omap.2", "i2c_ick", &i2c2_ick, CK_343X),
+ CLK("i2c_omap.1", "i2c_ick", &i2c1_ick, CK_343X),
+ CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
+ CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
+ CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
+ CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
+ CLK("omap-mcbsp.5", "mcbsp_ick", &mcbsp5_ick, CK_343X),
+ CLK("omap-mcbsp.1", "mcbsp_ick", &mcbsp1_ick, CK_343X),
+ CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
+ CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
+ CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
+ CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
+ CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
+ CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
+ CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
+ CLK(NULL, "rng_ick", &rng_ick, CK_343X),
+ CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
+ CLK(NULL, "des1_ick", &des1_ick, CK_343X),
+ CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
+ CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
+ CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
+ CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
+ CLK(NULL, "dss_ick", &dss_ick, CK_343X),
+ CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
+ CLK(NULL, "cam_ick", &cam_ick, CK_343X),
+ CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
+ CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
+ CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
+ CLK(NULL, "usbhost_sar_fck", &usbhost_sar_fck, CK_3430ES2),
+ CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
+ CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
+ CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
+ CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
+ CLK(NULL, "wdt2_fck", &wdt2_fck, CK_343X),
+ CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
+ CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
+ CLK(NULL, "wdt2_ick", &wdt2_ick, CK_343X),
+ CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
+ CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
+ CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
+ CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
+ CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
+ CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
+ CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
+ CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
+ CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
+ CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
+ CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
+ CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
+ CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
+ CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
+ CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
+ CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
+ CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
+ CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
+ CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
+ CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
+ CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
+ CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
+ CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
+ CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
+ CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
+ CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
+ CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
+ CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
+ CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
+ CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
+ CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
+ CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
+ CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
+ CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
+ CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
+ CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
+ CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
+ CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
+ CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
+ CLK("omap-mcbsp.2", "mcbsp_ick", &mcbsp2_ick, CK_343X),
+ CLK("omap-mcbsp.3", "mcbsp_ick", &mcbsp3_ick, CK_343X),
+ CLK("omap-mcbsp.4", "mcbsp_ick", &mcbsp4_ick, CK_343X),
+ CLK("omap-mcbsp.2", "mcbsp_fck", &mcbsp2_fck, CK_343X),
+ CLK("omap-mcbsp.3", "mcbsp_fck", &mcbsp3_fck, CK_343X),
+ CLK("omap-mcbsp.4", "mcbsp_fck", &mcbsp4_fck, CK_343X),
+ CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
+ CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
+ CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
+ CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
+ CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
+ CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
+ CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
+ CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
+ CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
+ CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
+ CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
+ CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
+};
+
/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
#define DPLL_AUTOIDLE_DISABLE 0x0
#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
@@ -453,26 +688,13 @@ arch_initcall(omap2_clk_arch_init);
int __init omap2_clk_init(void)
{
/* struct prcm_config *prcm; */
- struct clk **clkp;
+ struct omap_clk *c;
/* u32 clkrate; */
u32 cpu_clkflg;
- /* REVISIT: Ultimately this will be used for multiboot */
-#if 0
- if (cpu_is_omap242x()) {
- cpu_mask = RATE_IN_242X;
- cpu_clkflg = CLOCK_IN_OMAP242X;
- clkp = onchip_24xx_clks;
- } else if (cpu_is_omap2430()) {
- cpu_mask = RATE_IN_243X;
- cpu_clkflg = CLOCK_IN_OMAP243X;
- clkp = onchip_24xx_clks;
- }
-#endif
if (cpu_is_omap34xx()) {
cpu_mask = RATE_IN_343X;
- cpu_clkflg = CLOCK_IN_OMAP343X;
- clkp = onchip_34xx_clks;
+ cpu_clkflg = CK_343X;
/*
* Update this if there are further clock changes between ES2
@@ -480,23 +702,21 @@ int __init omap2_clk_init(void)
*/
if (omap_rev() == OMAP3430_REV_ES1_0) {
/* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
- cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
+ cpu_clkflg |= CK_3430ES1;
} else {
cpu_mask |= RATE_IN_3430ES2;
- cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
+ cpu_clkflg |= CK_3430ES2;
}
}
clk_init(&omap2_clk_functions);
- for (clkp = onchip_34xx_clks;
- clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
- clkp++) {
- if ((*clkp)->flags & cpu_clkflg) {
- clk_register(*clkp);
- omap2_init_clk_clkdm(*clkp);
+ for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+ if (c->cpu & cpu_clkflg) {
+ clkdev_add(&c->lk);
+ clk_register(c->lk.clk);
+ omap2_init_clk_clkdm(c->lk.clk);
}
- }
/* REVISIT: Not yet ready for OMAP3 */
#if 0
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index dcacec84f8c..6bd8c6d5a4e 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -57,14 +57,14 @@ static struct clk omap_32k_fck = {
.name = "omap_32k_fck",
.ops = &clkops_null,
.rate = 32768,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
static struct clk secure_32k_fck = {
.name = "secure_32k_fck",
.ops = &clkops_null,
.rate = 32768,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
/* Virtual source clocks for osc_sys_ck */
@@ -72,42 +72,42 @@ static struct clk virt_12m_ck = {
.name = "virt_12m_ck",
.ops = &clkops_null,
.rate = 12000000,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
static struct clk virt_13m_ck = {
.name = "virt_13m_ck",
.ops = &clkops_null,
.rate = 13000000,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
static struct clk virt_16_8m_ck = {
.name = "virt_16_8m_ck",
.ops = &clkops_null,
.rate = 16800000,
- .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
static struct clk virt_19_2m_ck = {
.name = "virt_19_2m_ck",
.ops = &clkops_null,
.rate = 19200000,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
static struct clk virt_26m_ck = {
.name = "virt_26m_ck",
.ops = &clkops_null,
.rate = 26000000,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
static struct clk virt_38_4m_ck = {
.name = "virt_38_4m_ck",
.ops = &clkops_null,
.rate = 38400000,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
};
static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -160,7 +160,7 @@ static struct clk osc_sys_ck = {
.clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
.clksel = osc_sys_clksel,
/* REVISIT: deal with autoextclkmode? */
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
+ .flags = RATE_FIXED | RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -185,21 +185,21 @@ static struct clk sys_ck = {
.clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
.clksel_mask = OMAP_SYSCLKDIV_MASK,
.clksel = sys_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
static struct clk sys_altclk = {
.name = "sys_altclk",
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
};
/* Optional external clock input for some McBSPs */
static struct clk mcbsp_clks = {
.name = "mcbsp_clks",
.ops = &clkops_null,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
};
/* PRM EXTERNAL CLOCK OUTPUT */
@@ -210,7 +210,6 @@ static struct clk sys_clkout1 = {
.parent = &osc_sys_ck,
.enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
.recalc = &followparent_recalc,
};
@@ -275,7 +274,7 @@ static struct clk dpll1_ck = {
.ops = &clkops_null,
.parent = &sys_ck,
.dpll_data = &dpll1_dd,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.round_rate = &omap2_dpll_round_rate,
.recalc = &omap3_dpll_recalc,
};
@@ -288,7 +287,7 @@ static struct clk dpll1_x2_ck = {
.name = "dpll1_x2_ck",
.ops = &clkops_null,
.parent = &dpll1_ck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -310,7 +309,7 @@ static struct clk dpll1_x2m2_ck = {
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
.clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
.clksel = div16_dpll1_x2m2_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -343,7 +342,7 @@ static struct clk dpll2_ck = {
.ops = &clkops_noncore_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll2_dd,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.round_rate = &omap2_dpll_round_rate,
.recalc = &omap3_dpll_recalc,
};
@@ -366,7 +365,7 @@ static struct clk dpll2_m2_ck = {
OMAP3430_CM_CLKSEL2_PLL),
.clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
.clksel = div16_dpll2_m2x2_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -396,7 +395,7 @@ static struct clk dpll3_ck = {
.ops = &clkops_null,
.parent = &sys_ck,
.dpll_data = &dpll3_dd,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.round_rate = &omap2_dpll_round_rate,
.recalc = &omap3_dpll_recalc,
};
@@ -409,7 +408,7 @@ static struct clk dpll3_x2_ck = {
.name = "dpll3_x2_ck",
.ops = &clkops_null,
.parent = &dpll3_ck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -466,7 +465,7 @@ static struct clk dpll3_m2_ck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
.clksel = div31_dpll3m2_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -483,7 +482,7 @@ static struct clk core_ck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
.clksel = core_ck_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -500,7 +499,7 @@ static struct clk dpll3_m2x2_ck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
.clksel = dpll3_m2x2_ck_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -519,7 +518,7 @@ static struct clk dpll3_m3_ck = {
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_DIV_DPLL3_MASK,
.clksel = div16_dpll3_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -530,7 +529,7 @@ static struct clk dpll3_m3x2_ck = {
.parent = &dpll3_m3_ck,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .flags = RATE_PROPAGATES | INVERT_ENABLE,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -548,7 +547,7 @@ static struct clk emu_core_alwon_ck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
.clksel = emu_core_alwon_ck_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -579,7 +578,7 @@ static struct clk dpll4_ck = {
.ops = &clkops_noncore_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll4_dd,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.round_rate = &omap2_dpll_round_rate,
.recalc = &omap3_dpll_recalc,
};
@@ -593,7 +592,7 @@ static struct clk dpll4_x2_ck = {
.name = "dpll4_x2_ck",
.ops = &clkops_null,
.parent = &dpll4_ck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -611,7 +610,7 @@ static struct clk dpll4_m2_ck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
.clksel_mask = OMAP3430_DIV_96M_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -622,7 +621,7 @@ static struct clk dpll4_m2x2_ck = {
.parent = &dpll4_m2_ck,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .flags = RATE_PROPAGATES | INVERT_ENABLE,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -640,7 +639,7 @@ static struct clk omap_96m_alwon_fck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.clksel = omap_96m_alwon_fck_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -648,7 +647,7 @@ static struct clk omap_96m_fck = {
.name = "omap_96m_fck",
.ops = &clkops_null,
.parent = &omap_96m_alwon_fck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &followparent_recalc,
};
@@ -666,7 +665,7 @@ static struct clk cm_96m_fck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.clksel = cm_96m_fck_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -679,7 +678,7 @@ static struct clk dpll4_m3_ck = {
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_TV_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -691,7 +690,7 @@ static struct clk dpll4_m3x2_ck = {
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .flags = RATE_PROPAGATES | INVERT_ENABLE,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -709,7 +708,7 @@ static struct clk virt_omap_54m_fck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.clksel = virt_omap_54m_fck_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -736,7 +735,7 @@ static struct clk omap_54m_fck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_54M,
.clksel = omap_54m_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -763,7 +762,7 @@ static struct clk omap_48m_fck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_48M,
.clksel = omap_48m_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -772,7 +771,7 @@ static struct clk omap_12m_fck = {
.ops = &clkops_null,
.parent = &omap_48m_fck,
.fixed_div = 4,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_fixed_divisor_recalc,
};
@@ -785,7 +784,7 @@ static struct clk dpll4_m4_ck = {
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -796,7 +795,7 @@ static struct clk dpll4_m4x2_ck = {
.parent = &dpll4_m4_ck,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .flags = RATE_PROPAGATES | INVERT_ENABLE,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -809,7 +808,7 @@ static struct clk dpll4_m5_ck = {
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -820,7 +819,7 @@ static struct clk dpll4_m5x2_ck = {
.parent = &dpll4_m5_ck,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .flags = RATE_PROPAGATES | INVERT_ENABLE,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -833,7 +832,7 @@ static struct clk dpll4_m6_ck = {
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_DIV_DPLL4_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -845,7 +844,7 @@ static struct clk dpll4_m6x2_ck = {
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .flags = RATE_PROPAGATES | INVERT_ENABLE,
.recalc = &omap3_clkoutx2_recalc,
};
@@ -853,7 +852,7 @@ static struct clk emu_per_alwon_ck = {
.name = "emu_per_alwon_ck",
.ops = &clkops_null,
.parent = &dpll4_m6x2_ck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &followparent_recalc,
};
@@ -885,7 +884,7 @@ static struct clk dpll5_ck = {
.ops = &clkops_noncore_dpll_ops,
.parent = &sys_ck,
.dpll_data = &dpll5_dd,
- .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.round_rate = &omap2_dpll_round_rate,
.recalc = &omap3_dpll_recalc,
};
@@ -903,7 +902,7 @@ static struct clk dpll5_m2_ck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
.clksel_mask = OMAP3430ES2_DIV_120M_MASK,
.clksel = div16_dpll5_clksel,
- .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -921,7 +920,7 @@ static struct clk omap_120m_fck = {
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
.clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
.clksel = omap_120m_fck_clksel,
- .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -964,7 +963,7 @@ static struct clk clkout2_src_ck = {
.clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
.clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
.clksel = clkout2_src_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -989,7 +988,6 @@ static struct clk sys_clkout2 = {
.clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
.clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
- .flags = CLOCK_IN_OMAP343X,
.recalc = &omap2_clksel_recalc,
};
@@ -999,7 +997,7 @@ static struct clk corex2_fck = {
.name = "corex2_fck",
.ops = &clkops_null,
.parent = &dpll3_m2x2_ck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &followparent_recalc,
};
@@ -1022,7 +1020,7 @@ static struct clk dpll1_fck = {
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
.clksel = div2_core_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -1046,7 +1044,7 @@ static struct clk mpu_ck = {
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
.clksel = mpu_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.clkdm_name = "mpu_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1071,7 +1069,7 @@ static struct clk arm_fck = {
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
.clksel = arm_fck_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -1085,7 +1083,7 @@ static struct clk emu_mpu_alwon_ck = {
.name = "emu_mpu_alwon_ck",
.ops = &clkops_null,
.parent = &mpu_ck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &followparent_recalc,
};
@@ -1097,7 +1095,7 @@ static struct clk dpll2_fck = {
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
.clksel = div2_core_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -1125,7 +1123,7 @@ static struct clk iva2_ck = {
OMAP3430_CM_IDLEST_PLL),
.clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
.clksel = iva2_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.clkdm_name = "iva2_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1140,7 +1138,7 @@ static struct clk l3_ick = {
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_L3_MASK,
.clksel = div2_core_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.clkdm_name = "core_l3_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1158,7 +1156,7 @@ static struct clk l4_ick = {
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_L4_MASK,
.clksel = div2_l3_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
@@ -1177,7 +1175,6 @@ static struct clk rm_ick = {
.clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_RM_MASK,
.clksel = div2_l4_clksel,
- .flags = CLOCK_IN_OMAP343X,
.recalc = &omap2_clksel_recalc,
};
@@ -1198,7 +1195,6 @@ static struct clk gfx_l3_ck = {
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
@@ -1210,7 +1206,7 @@ static struct clk gfx_l3_fck = {
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_l3_clksel,
- .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.clkdm_name = "gfx_3430es1_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1219,7 +1215,6 @@ static struct clk gfx_l3_ick = {
.name = "gfx_l3_ick",
.ops = &clkops_null,
.parent = &gfx_l3_ck,
- .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc,
};
@@ -1231,7 +1226,6 @@ static struct clk gfx_cg1_ck = {
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc,
};
@@ -1243,7 +1237,6 @@ static struct clk gfx_cg2_ck = {
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc,
};
@@ -1277,7 +1270,6 @@ static struct clk sgx_fck = {
.clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
.clksel = sgx_clksel,
- .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "sgx_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1289,7 +1281,6 @@ static struct clk sgx_ick = {
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
.clkdm_name = "sgx_clkdm",
.recalc = &followparent_recalc,
};
@@ -1303,7 +1294,6 @@ static struct clk d2d_26m_fck = {
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
.clkdm_name = "d2d_clkdm",
.recalc = &followparent_recalc,
};
@@ -1324,7 +1314,6 @@ static struct clk gpt10_fck = {
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1339,7 +1328,6 @@ static struct clk gpt11_fck = {
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1350,7 +1338,6 @@ static struct clk cpefuse_fck = {
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
.recalc = &followparent_recalc,
};
@@ -1360,7 +1347,6 @@ static struct clk ts_fck = {
.parent = &omap_32k_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
.recalc = &followparent_recalc,
};
@@ -1370,7 +1356,6 @@ static struct clk usbtll_fck = {
.parent = &omap_120m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
.recalc = &followparent_recalc,
};
@@ -1380,7 +1365,7 @@ static struct clk core_96m_fck = {
.name = "core_96m_fck",
.ops = &clkops_null,
.parent = &omap_96m_fck,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = RATE_PROPAGATES,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
@@ -1392,7 +1377,6 @@ static struct clk mmchs3_fck = {
.parent = &core_96m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIF