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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-07 11:01:36 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-08-26 16:43:34 -0700 |
| commit | 71e55b36b5aa7ffe749970afc4056e66518766cc (patch) | |
| tree | 281134ca6694f94f3e9da84aff2168fab453a9af | |
| parent | 46e21869656d0e3d2a2949a8451cb03a6c75c5ee (diff) | |
drm/i915/edp: Flush the write before waiting for PLLs
commit 5ddb954b9ee50824977d2931e0ff58b3050b337d upstream.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c234c6a86cf..66eb4587b31 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1470,6 +1470,7 @@ static void ironlake_enable_pll_edp (struct drm_crtc *crtc) dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); + POSTING_READ(DP_A); udelay(200); } |