Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc

* 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc: (25 commits)
  [POWERPC] 85xx: Added needed MPC85xx PCI device IDs
  [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs
  [POWERPC] 85xxCDS: MPC8548 DTS cleanup.
  [POWERPC] 85xxCDS: Misc 8548 PCI Corrections.
  [POWERPC] 85xxCDS: Delay 8259 cascade hookup.
  [POWERPC] 85xxCDS: Make sure restart resets the PCI bus.
  [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line.
  [POWERPC] FSL: Add support for PCI-X controllers
  [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB
  [POWERPC] Provide ability to setup P2P bridge registers from struct resource
  [POWERPC] Add basic PCI/PCI Express support for 8544DS board
  [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime
  [POWERPC] Removed setup_indirect_pci_nomap
  [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS
  [POWERPC] 85xx: Added 8568 PCIe support
  [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected
  [POWERPC] Add basic PCI node for mpc8568mds board
  [POWERPC] Use Freescale pci/pcie common code for 85xx boards
  [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree
  [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node
  ...

45 files changed, 1660 insertions, 840 deletions

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 853c282da22..00099efe0e9 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI
 	default y if 40x || 44x
 	default n
 
-config PPC_INDIRECT_PCI_BE
-	bool
-	depends PPC_INDIRECT_PCI
-	default n
-
 config EISA
 	bool
 
@@ -425,6 +420,10 @@ config SBUS
 config FSL_SOC
 	bool
 
+config FSL_PCI
+ 	bool
+	select PPC_INDIRECT_PCI
+
 # Yes MCA RS/6000s exist but Linux-PPC does not currently support any
 config MCA
 	bool
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index a1533cc07d0..c5adbe40364 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -178,7 +178,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8500 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 4fc0c4d34aa..f158ed781ba 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -154,7 +154,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8500 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 447c03ffabb..7c4beff3e20 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -123,7 +123,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8500 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index ae9bca57545..502f47c0179 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -197,7 +197,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8500 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
@@ -222,7 +222,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8600 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index f636528a3c7..0b8387141d8 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -154,7 +154,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8600 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 310e877826b..481099756e4 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -241,7 +241,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8500 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
@@ -301,7 +301,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8600 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 1e914f31dd9..e3f7c128206 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -169,7 +169,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8500 100>;
-			compatible = "83xx";
+			compatible = "fsl,mpc8349-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 364a969f5c2..fc8dff9f620 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -258,7 +258,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 070206fffe8..fb0b647f8c2 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -193,7 +193,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc8540-pci";
 			device_type = "pci";
 
 			i8259@19000 {
@@ -230,7 +230,7 @@
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <9000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc8540-pci";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 82859259246..4a900c6df76 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -137,6 +137,217 @@
 			interrupt-parent = <&mpic>;
 		};
 
+		pci@8000 {
+			compatible = "fsl,mpc8540-pci";
+			device_type = "pci";
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+
+				/* IDSEL 0x11 J17 Slot 1 */
+				8800 0 0 1 &mpic 2 1
+				8800 0 0 2 &mpic 3 1
+				8800 0 0 3 &mpic 4 1
+				8800 0 0 4 &mpic 1 1
+
+				/* IDSEL 0x12 J16 Slot 2 */
+
+				9000 0 0 1 &mpic 3 1
+				9000 0 0 2 &mpic 4 1
+				9000 0 0 3 &mpic 2 1
+				9000 0 0 4 &mpic 1 1>;
+
+			interrupt-parent = <&mpic>;
+			interrupts = <18 2>;
+			bus-range = <0 ff>;
+			ranges = <02000000 0 80000000 80000000 0 10000000
+				  01000000 0 00000000 e2000000 0 00800000>;
+			clock-frequency = <3f940aa>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <8000 1000>;
+		};
+
+		pcie@9000 {
+			compatible = "fsl,mpc8548-pcie";
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <9000 1000>;
+			bus-range = <0 ff>;
+			ranges = <02000000 0 90000000 90000000 0 10000000
+				  01000000 0 00000000 e3000000 0 00800000>;
+			clock-frequency = <1fca055>;
+			interrupt-parent = <&mpic>;
+			interrupts = <1a 2>;
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x0 */
+				0000 0 0 1 &mpic 4 1
+				0000 0 0 2 &mpic 5 1
+				0000 0 0 3 &mpic 6 1
+				0000 0 0 4 &mpic 7 1
+				>;
+		};
+
+		pcie@a000 {
+			compatible = "fsl,mpc8548-pcie";
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <a000 1000>;
+			bus-range = <0 ff>;
+			ranges = <02000000 0 a0000000 a0000000 0 10000000
+				  01000000 0 00000000 e2800000 0 00800000>;
+			clock-frequency = <1fca055>;
+			interrupt-parent = <&mpic>;
+			interrupts = <19 2>;
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x0 */
+				0000 0 0 1 &mpic 0 1
+				0000 0 0 2 &mpic 1 1
+				0000 0 0 3 &mpic 2 1
+				0000 0 0 4 &mpic 3 1
+				>;
+		};
+
+		pcie@b000 {
+			compatible = "fsl,mpc8548-pcie";
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <b000 1000>;
+			bus-range = <0 ff>;
+			ranges = <02000000 0 b0000000 b0000000 0 10000000
+				  01000000 0 00000000 e3800000 0 00800000>;
+			clock-frequency = <1fca055>;
+			interrupt-parent = <&mpic>;
+			interrupts = <1b 2>;
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+
+				// IDSEL 0x1a
+				d000 0 0 1 &i8259 6 2
+				d000 0 0 2 &i8259 3 2
+				d000 0 0 3 &i8259 4 2
+				d000 0 0 4 &i8259 5 2
+
+				// IDSEL 0x1b
+				d800 0 0 1 &i8259 5 2
+				d800 0 0 2 &i8259 0 0
+				d800 0 0 3 &i8259 0 0
+				d800 0 0 4 &i8259 0 0
+
+				// IDSEL 0x1c  USB
+				e000 0 0 1 &i8259 9 2
+				e000 0 0 2 &i8259 a 2
+				e000 0 0 3 &i8259 c 2
+				e000 0 0 4 &i8259 7 2
+
+				// IDSEL 0x1d  Audio
+				e800 0 0 1 &i8259 9 2
+				e800 0 0 2 &i8259 a 2
+				e800 0 0 3 &i8259 b 2
+				e800 0 0 4 &i8259 0 0
+
+				// IDSEL 0x1e Legacy
+				f000 0 0 1 &i8259 c 2
+				f000 0 0 2 &i8259 0 0
+				f000 0 0 3 &i8259 0 0
+				f000 0 0 4 &i8259 0 0
+
+				// IDSEL 0x1f IDE/SATA
+				f800 0 0 1 &i8259 6 2
+				f800 0 0 2 &i8259 0 0
+				f800 0 0 3 &i8259 0 0
+				f800 0 0 4 &i8259 0 0
+			>;
+			uli1575@0 {
+				reg = <0 0 0 0 0>;
+				#size-cells = <2>;
+				#address-cells = <3>;
+				ranges = <02000000 0 b0000000
+					  02000000 0 b0000000
+					  0 10000000
+					  01000000 0 00000000
+					  01000000 0 00000000
+					  0 00080000>;
+
+				pci_bridge@0 {
+					reg = <0 0 0 0 0>;
+					#size-cells = <2>;
+					#address-cells = <3>;
+					ranges = <02000000 0 b0000000
+						  02000000 0 b0000000
+						  0 20000000
+						  01000000 0 00000000
+						  01000000 0 00000000
+						  0 00100000>;
+
+					isa@1e {
+						device_type = "isa";
+						#interrupt-cells = <2>;
+						#size-cells = <1>;
+						#address-cells = <2>;
+						reg = <f000 0 0 0 0>;
+						ranges = <1 0 01000000 0 0
+							  00001000>;
+						interrupt-parent = <&i8259>;
+
+						i8259: interrupt-controller@20 {
+							reg = <1 20 2
+							       1 a0 2
+							       1 4d0 2>;
+							clock-frequency = <0>;
+							interrupt-controller;
+							device_type = "interrupt-controller";
+							#address-cells = <0>;
+							#interrupt-cells = <2>;
+							built-in;
+							compatible = "chrp,iic";
+							interrupts = <9 2>;
+							interrupt-parent =
+								<&mpic>;
+						};
+
+						i8042@60 {
+							#size-cells = <0>;
+							#address-cells = <1>;
+							reg = <1 60 1 1 64 1>;
+							interrupts = <1 3 c 3>;
+							interrupt-parent =
+								<&i8259>;
+
+							keyboard@0 {
+								reg = <0>;
+								compatible = "pnpPNP,303";
+							};
+
+							mouse@1 {
+								reg = <1>;
+								compatible = "pnpPNP,f03";
+							};
+						};
+
+						rtc@70 {
+							compatible =
+								"pnpPNP,b00";
+							reg = <1 70 2>;
+						};
+
+						gpio@400 {
+							reg = <1 400 80>;
+						};
+					};
+				};
+			};
+
+		};
+
 		mpic: pic@40000 {
 			clock-frequency = <0>;
 			interrupt-controller;
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b66cd..d215d21fff4 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
 /*
- * MPC8555 CDS Device Tree Source
+ * MPC8548 CDS Device Tree Source
  *
  * Copyright 2006 Freescale Semiconductor Inc.
  *
@@ -44,8 +44,14 @@
 		#size-cells = <1>;
 		#interrupt-cells = <2>;
 		device_type = "soc";
-		ranges = <0 e0000000 00100000>;
-		reg = <e0000000 00100000>;	// CCSRBAR 1M
+		ranges = <00001000 e0001000 000ff000
+			  80000000 80000000 10000000
+			  e2000000 e2000000 00800000
+			  90000000 90000000 10000000
+			  e2800000 e2800000 00800000
+			  a0000000 a0000000 20000000
+		          e3000000 e3000000 01000000>;
+		reg = <e0000000 00001000>;	// CCSRBAR
 		bus-frequency = <0>;
 
 		memory-controller@2000 {
@@ -162,8 +168,8 @@
 		serial@4500 {
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>; 	// reg base, size
-			clock-frequency = <0>; 	// should we fill in in uboot?
+			reg = <4500 100>;	// reg base, size
+			clock-frequency = <0>;	// should we fill in in uboot?
 			interrupts = <2a 2>;
 			interrupt-parent = <&mpic>;
 		};
@@ -172,7 +178,7 @@
 			device_type = "serial";
 			compatible = "ns16550";
 			reg = <4600 100>;	// reg base, size
-			clock-frequency = <0>; 	// should we fill in in uboot?
+			clock-frequency = <0>;	// should we fill in in uboot?
 			interrupts = <2a 2>;
 			interrupt-parent = <&mpic>;
 		};
@@ -183,77 +189,154 @@
 			fsl,has-rstcr;
 		};
 
-		pci1: pci@8000 {
-			interrupt-map-mask = <1f800 0 0 7>;
+		pci@8000 {
+			interrupt-map-mask = <f800 0 0 7>;
 			interrupt-map = <
+				/* IDSEL 0x4 (PCIX Slot 2) */
+				02000 0 0 1 &mpic 0 1
+				02000 0 0 2 &mpic 1 1
+				02000 0 0 3 &mpic 2 1
+				02000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x5 (PCIX Slot 3) */
+				02800 0 0 1 &mpic 1 1
+				02800 0 0 2 &mpic 2 1
+				02800 0 0 3 &mpic 3 1
+				02800 0 0 4 &mpic 0 1
+
+				/* IDSEL 0x6 (PCIX Slot 4) */
+				03000 0 0 1 &mpic 2 1
+				03000 0 0 2 &mpic 3 1
+				03000 0 0 3 &mpic 0 1
+				03000 0 0 4 &mpic 1 1
+
+				/* IDSEL 0x8 (PCIX Slot 5) */
+				04000 0 0 1 &mpic 0 1
+				04000 0 0 2 &mpic 1 1
+				04000 0 0 3 &mpic 2 1
+				04000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0xC (Tsi310 bridge) */
+				06000 0 0 1 &mpic 0 1
+				06000 0 0 2 &mpic 1 1
+				06000 0 0 3 &mpic 2 1
+				06000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x14 (Slot 2) */
+				0a000 0 0 1 &mpic 0 1
+				0a000 0 0 2 &mpic 1 1
+				0a000 0 0 3 &mpic 2 1
+				0a000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x15 (Slot 3) */
+				0a800 0 0 1 &mpic 1 1
+				0a800 0 0 2 &mpic 2 1
+				0a800 0 0 3 &mpic 3 1
+				0a800 0 0 4 &mpic 0 1
+
+				/* IDSEL 0x16 (Slot 4) */
+				0b000 0 0 1 &mpic 2 1
+				0b000 0 0 2 &mpic 3 1
+				0b000 0 0 3 &mpic 0 1
+				0b000 0 0 4 &mpic 1 1
+
+				/* IDSEL 0x18 (Slot 5) */
+				0c000 0 0 1 &mpic 0 1
+				0c000 0 0 2 &mpic 1 1
+				0c000 0 0 3 &mpic 2 1
+				0c000 0 0 4 &mpic 3 1
+
+				/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+				0E000 0 0 1 &mpic 0 1
+				0E000 0 0 2 &mpic 1 1
+				0E000 0 0 3 &mpic 2 1
+				0E000 0 0 4 &mpic 3 1>;
 
-				/* IDSEL 0x10 */
-				08000 0 0 1 &mpic 0 1
-				08000 0 0 2 &mpic 1 1
-				08000 0 0 3 &mpic 2 1
-				08000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x11 */
-				08800 0 0 1 &mpic 0 1
-				08800 0 0 2 &mpic 1 1
-				08800 0 0 3 &mpic 2 1
-				08800 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x12 (Slot 1) */
-				09000 0 0 1 &mpic 0 1
-				09000 0 0 2 &mpic 1 1
-				09000 0 0 3 &mpic 2 1
-				09000 0 0 4 &mpic 3 1
-
-				/* IDSEL 0x13 (Slot 2) */
-				09800 0 0 1 &mpic 1 1
-				09800 0 0 2 &mpic 2 1
-				09800 0 0 3 &mpic 3 1
-				09800 0 0 4 &mpic 0 1
-
-				/* IDSEL 0x14 (Slot 3) */
-				0a000 0 0 1 &mpic 2 1
-				0a000 0 0 2 &mpic 3 1
-				0a000 0 0 3 &mpic 0 1
-				0a000 0 0 4 &mpic 1 1
-
-				/* IDSEL 0x15 (Slot 4) */
-				0a800 0 0 1 &mpic 3 1
-				0a800 0 0 2 &mpic 0 1
-				0a800 0 0 3 &mpic 1 1
-				0a800 0 0 4 &mpic 2 1
-
-				/* Bus 1 (Tundra Bridge) */
-				/* IDSEL 0x12 (ISA bridge) */
-				19000 0 0 1 &mpic 0 1
-				19000 0 0 2 &mpic 1 1
-				19000 0 0 3 &mpic 2 1
-				19000 0 0 4 &mpic 3 1>;
 			interrupt-parent = <&mpic>;
 			interrupts = <18 2>;
 			bus-range = <0 0>;
-			ranges = <02000000 0 80000000 80000000 0 20000000
-				  01000000 0 00000000 e2000000 0 00100000>;
+			ranges = <02000000 0 80000000 80000000 0 10000000
+				  01000000 0 00000000 e2000000 0 00800000>;
 			clock-frequency = <3f940aa>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <8000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 			device_type = "pci";
 
-			i8259@19000 {
-				clock-frequency = <0>;
-				interrupt-controller;
-				device_type = "interrupt-controller";
-				reg = <19000 0 0 0 1>;
-				#address-cells = <0>;
-				#interrupt-cells = <2>;
-				built-in;
-				compatible = "chrp,iic";
-				big-endian;
-				interrupts = <1>;
-				interrupt-parent = <&pci1>;
+			pci_bridge@1c {
+				interrupt-map-mask = <f800 0 0 7>;
+				interrupt-map = <
+
+					/* IDSEL 0x00 (PrPMC Site) */
+					0000 0 0 1 &mpic 0 1
+					0000 0 0 2 &mpic 1 1
+					0000 0 0 3 &mpic 2 1
+					0000 0 0 4 &mpic 3 1
+
+					/* IDSEL 0x04 (VIA chip) */
+					2000 0 0 1 &mpic 0 1
+					2000 0 0 2 &mpic 1 1
+					2000 0 0 3 &mpic 2 1
+					2000 0 0 4 &mpic 3 1
+
+					/* IDSEL 0x05 (8139) */
+					2800 0 0 1 &mpic 1 1
+
+					/* IDSEL 0x06 (Slot 6) */
+					3000 0 0 1 &mpic 2 1
+					3000 0 0 2 &mpic 3 1
+					3000 0 0 3 &mpic 0 1
+					3000 0 0 4 &mpic 1 1
+
+					/* IDESL 0x07 (Slot 7) */
+					3800 0 0 1 &mpic 3 1
+					3800 0 0 2 &mpic 0 1
+					3800 0 0 3 &mpic 1 1
+					3800 0 0 4 &mpic 2 1>;
+
+				reg = <e000 0 0 0 0>;
+				#interrupt-cells = <1>;
+				#size-cells = <2>;
+				#address-cells = <3>;
+				ranges = <02000000 0 80000000
+					  02000000 0 80000000
+					  0 20000000
+					  01000000 0 00000000
+					  01000000 0 00000000
+					  0 00080000>;
+				clock-frequency = <1fca055>;
+
+				isa@4 {
+					device_type = "isa";
+					#interrupt-cells = <2>;
+					#size-cells = <1>;
+					#address-cells = <2>;
+					reg = <2000 0 0 0 0>;
+					ranges = <1 0 01000000 0 0 00001000>;
+					interrupt-parent = <&i8259>;
+
+					i8259: interrupt-controller@20 {
+						clock-frequency = <0>;
+						interrupt-controller;
+						device_type = "interrupt-controller";
+						reg = <1 20 2
+						       1 a0 2
+						       1 4d0 2>;
+						#address-cells = <0>;
+						#interrupt-cells = <2>;
+						built-in;
+						compatible = "chrp,iic";
+						interrupts = <0 1>;
+						interrupt-parent = <&mpic>;
+					};
+
+					rtc@70 {
+						compatible = "pnpPNP,b00";
+						reg = <1 70 2>;
+					};
+				};
 			};
 		};
 
@@ -263,20 +346,45 @@
 
 				/* IDSEL 0x15 */
 				a800 0 0 1 &mpic b 1
-				a800 0 0 2 &mpic b 1
-				a800 0 0 3 &mpic b 1
-				a800 0 0 4 &mpic b 1>;
+				a800 0 0 2 &mpic 1 1
+				a800 0 0 3 &mpic 2 1
+				a800 0 0 4 &mpic 3 1>;
+
 			interrupt-parent = <&mpic>;
 			interrupts = <19 2>;
 			bus-range = <0 0>;
-			ranges = <02000000 0 a0000000 a0000000 0 20000000
-				  01000000 0 00000000 e3000000 0 00100000>;
+			ranges = <02000000 0 90000000 90000000 0 10000000
+				  01000000 0 00000000 e2800000 0 00800000>;
 			clock-frequency = <3f940aa>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			reg = <9000 1000>;
-			compatible = "85xx";
+			compatible = "fsl,mpc8540-pci";
+			device_type = "pci";
+		};
+		/* PCI Express */
+		pcie@a000 {
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+
+				/* IDSEL 0x0 (PEX) */
+				00000 0 0 1 &mpic 0 1
+				00000 0 0 2 &mpic 1 1
+				00000 0 0 3 &mpic 2 1
+				00000 0 0 4 &mpic 3 1>;
+
+			interrupt-parent = <&mpic>;
+			interrupts = <1a 2>;
+			bus-range = <0 ff>;
+			ranges = <02000000 0 a0000000 a0000000 0 20000000
+				  01000000 0 00000000 e3000000 0 08000000>;
+			clock-frequency = <1fca055>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			reg = <a000 1000>;
+			compatible = "fsl,mpc8548-pcie";
 			device_type = "pci";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 17e45d9a382..c3c88825212 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -193,7 +193,7 @@