diff options
| author | Chris Dearman <chris@mips.com> | 2007-05-08 16:09:13 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-05-11 14:28:31 +0100 |
| commit | 0b6249567b4ecf6e9d5a8efcf149f3e7cf788cc0 (patch) | |
| tree | dfb8d45357a9e8e3ad134f7eec87e7918132410e | |
| parent | d725cf3818b12a17d78b87a2de19e8eec17126ae (diff) | |
[MIPS] FPU hazard handling
Move FPU hazard handling to hazards.h and provide proper support for
MIPSR2 processors
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | include/asm-mips/fpu.h | 23 | ||||
| -rw-r--r-- | include/asm-mips/hazards.h | 32 |
2 files changed, 35 insertions, 20 deletions
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index b414a7d9db4..483685b1592 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -16,6 +16,7 @@ #include <asm/mipsregs.h> #include <asm/cpu.h> #include <asm/cpu-features.h> +#include <asm/hazards.h> #include <asm/bitops.h> #include <asm/processor.h> #include <asm/current.h> @@ -38,34 +39,16 @@ extern void _init_fpu(void); extern void _save_fp(struct task_struct *); extern void _restore_fp(struct task_struct *); -#if defined(CONFIG_CPU_SB1) -#define __enable_fpu_hazard() \ -do { \ - asm(".set push \n\t" \ - ".set mips64 \n\t" \ - ".set noreorder \n\t" \ - "ssnop \n\t" \ - "bnezl $0, .+4 \n\t" \ - "ssnop \n\t" \ - ".set pop"); \ -} while (0) -#else -#define __enable_fpu_hazard() \ -do { \ - asm("nop;nop;nop;nop"); /* max. hazard */ \ -} while (0) -#endif - #define __enable_fpu() \ do { \ set_c0_status(ST0_CU1); \ - __enable_fpu_hazard(); \ + enable_fpu_hazard(); \ } while (0) #define __disable_fpu() \ do { \ clear_c0_status(ST0_CU1); \ - /* We don't care about the c0 hazard here */ \ + disable_fpu_hazard(); \ } while (0) #define enable_fpu() \ diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index e50c77e69cb..1542f23ab9d 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -178,4 +178,36 @@ ASMMACRO(back_to_back_c0_hazard, #endif + +/* FPU hazards */ + +#if defined(CONFIG_CPU_SB1) +ASMMACRO(enable_fpu_hazard, + .set push; + .set mips64; + .set noreorder; + _ssnop; + bnezl $0,.+4; + _ssnop + .set pop +) +ASMMACRO(disable_fpu_hazard, +) + +#elif defined(CONFIG_CPU_MIPSR2) +ASMMACRO(enable_fpu_hazard, + _ehb +) +ASMMACRO(disable_fpu_hazard, + _ehb +) +#else +ASMMACRO(enable_fpu_hazard, + nop; nop; nop; nop +) +ASMMACRO(disable_fpu_hazard, + _ehb +) +#endif + #endif /* _ASM_HAZARDS_H */ |