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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-07 11:01:36 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-08-26 16:41:42 -0700 |
| commit | 592de9cc7e8c4886d05139771e748da2e9f13f4b (patch) | |
| tree | 5eea8fd58ee42b6d487179f1b5278d2f203046d5 | |
| parent | dbd7e1896a800f717d334c6c0d1a2afca62bca86 (diff) | |
drm/i915/edp: Flush the write before waiting for PLLs
commit 5ddb954b9ee50824977d2931e0ff58b3050b337d upstream.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 88d5e3ad48a..4f5c733ca97 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1402,6 +1402,7 @@ static void igdng_enable_pll_edp (struct drm_crtc *crtc) dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); + POSTING_READ(DP_A); udelay(200); } |