diff options
| author | Chaithrika U S <chaithrika@ti.com> | 2009-07-22 07:45:04 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-07-23 08:14:29 +0100 |
| commit | 06c71282a90470184a78f7f0ab0f7ce0fc1f69c8 (patch) | |
| tree | 535d93024bd5634dac94a981d060ccc78ee754c8 | |
| parent | b7d4de7ff03085fda8310b2983b907166dd40f43 (diff) | |
ASoC: tlv320aic3x: Enable PLL when not bypassed
PLL was not being enabled when it was not bypassed. This patch
enables the PLL when it is used. Additionally, it disables the PLL
when it is bypassed.
Without this patch, the audio on TI DM646x EVM and DM355 EVM
does not work properly. The bit clocks and the frame sync signals
from the codec are not correct and hence the playback/record are faster
than usual for most sample rates. The reason for this was that the PLL
was not enabled when it was not bypassed.
Tested on DM6467 EVM, playback tested on DM355 EVM.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| -rw-r--r-- | sound/soc/codecs/tlv320aic3x.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index ab099f48248..cb0d1bf34b5 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -767,6 +767,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; u16 pll_d = 1; + u8 reg; /* select data word length */ data = @@ -801,8 +802,16 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream, pll_q &= 0xf; aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); - } else + /* disable PLL if it is bypassed */ + reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); + aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE); + + } else { aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); + /* enable PLL when it is used */ + reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); + aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE); + } /* Route Left DAC to left channel input and * right DAC to right channel input */ |