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authorMagnus Damm <damm@opensource.se>2010-05-11 07:05:09 +0000
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 17:34:10 +0900
commitd40db0c4a63c3af44fd31a7c47cc4a11a44befc7 (patch)
treef456e74ede8b195fc6b8d36245cdb9e1322d8031
parentc77a9c3edee079fe0411d98cfb9d872bc336ee32 (diff)
sh: div4 reparent workaround
Update the div4 set_parent() callback to use the flags instead of name to determine parent index. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 17a73ad7a20..0b165f6ae08 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -168,7 +168,12 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
u32 value;
int ret;
- if (!strcmp("pll_clk", parent->name))
+ /* we really need a better way to determine parent index, but for
+ * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
+ * no CLK_ENABLE_ON_INIT means external clock...
+ */
+
+ if (parent->flags & CLK_ENABLE_ON_INIT)
value = __raw_readl(clk->enable_reg) & ~(1 << 7);
else
value = __raw_readl(clk->enable_reg) | (1 << 7);