diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-05-23 16:37:32 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-06-06 00:15:10 +0100 |
| commit | 5ee823507b3c7d2187df2160125a4f64232d3a60 (patch) | |
| tree | f5109154f9ea442581cf0000dd5c3faa3466310f | |
| parent | f3bf07b9a367c342bcbc9f47d525d3cf5e8b4f3b (diff) | |
[MIPS] Fix instable BogoMIPS on multi-issue processors.
Increase alignment of BogoMIPS loop to 8 bytes. Having the delay loop
overlap cache line boundaries may cause instable delays.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | include/asm-mips/delay.h | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h index 64dd45150f6..928f30f8c45 100644 --- a/include/asm-mips/delay.h +++ b/include/asm-mips/delay.h @@ -19,20 +19,22 @@ static inline void __delay(unsigned long loops) { if (sizeof(long) == 4) __asm__ __volatile__ ( - ".set\tnoreorder\n" - "1:\tbnez\t%0,1b\n\t" - "subu\t%0,1\n\t" - ".set\treorder" + " .set noreorder \n" + " .align 3 \n" + "1: bnez %0, 1b \n" + " subu %0, 1 \n" + " .set reorder \n" : "=r" (loops) : "0" (loops)); else if (sizeof(long) == 8) __asm__ __volatile__ ( - ".set\tnoreorder\n" - "1:\tbnez\t%0,1b\n\t" - "dsubu\t%0,1\n\t" - ".set\treorder" - :"=r" (loops) - :"0" (loops)); + " .set noreorder \n" + " .align 3 \n" + "1: bnez %0, 1b \n" + " dsubu %0, 1 \n" + " .set reorder \n" + : "=r" (loops) + : "0" (loops)); } |