diff options
| author | Carolyn Wyborny <carolyn.wyborny@intel.com> | 2011-06-25 13:18:12 +0000 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-08-29 14:08:09 -0700 |
| commit | 12361acf4d2ca536624e2b7237ce371b29704b30 (patch) | |
| tree | 1db5f8714781d39131eedfaf5d8fb5ca7772ac2c | |
| parent | 7b1ef6c0a199bd93899f167f459627dd9421913a (diff) | |
igb: Fix lack of flush after register write and before delay
commit 064b43304ed8ede8e13ff7b4338d09fd37bcffb1 upstream.
Register writes followed by a delay are required to have a flush
before the delay in order to commit the values to the register. Without
the flush, the code following the delay may not function correctly.
Reported-by: Tong Ho <tong.ho@ericsson.com>
Reported-by: Guenter Roeck <guenter.roeck@ericsson.com>
Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| -rw-r--r-- | drivers/net/igb/e1000_82575.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c index 33352ffa966..d617f2d8969 100644 --- a/drivers/net/igb/e1000_82575.c +++ b/drivers/net/igb/e1000_82575.c @@ -941,6 +941,7 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) ctrl |= E1000_CTRL_SLU; ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); wr32(E1000_CTRL, ctrl); + wrfl(); ret_val = igb_setup_serdes_link_82575(hw); if (ret_val) |