linux/include/asm-mips/cpu.h, branch v2.6.25.14

[MIPS] Alchemy: Au1210/Au1250 CPU support

2008-01-29T10:14:59Z

This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle

[MIPS] Convert list of CPU types from #define to enum.

2007-10-11T22:46:16Z

Signed-off-by: Ralf Baechle

[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

2007-10-11T22:46:05Z

It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle

[MIPS] Add support for BCM47XX CPUs.

2007-10-11T22:46:02Z

Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch Cc: Felix Fietkau Cc: Florian Schirmer Signed-off-by: Aurelien Jarno Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle

[MIPS] PMC MSP71xx mips common

2007-07-10T16:33:03Z

Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean Signed-off-by: Ralf Baechle

[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

2007-07-10T16:33:02Z

Signed-off-by: Fuxin Zhang Signed-off-by: Ralf Baechle

[MIPS] Enable support for the userlocal hardware register

2007-07-10T16:33:02Z

Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle

[MIPS] Add macros to encode processor revisions.

2007-07-06T15:17:11Z

Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: Ralf Baechle

[MIPS] Use the proper technical term for naming some of the cache macros.

2006-07-13T20:26:04Z

Signed-off-by: Ralf Baechle

[MIPS] Treat R14000 like R10000.

2006-05-31T23:28:35Z

Signed-off-by: Joshua Kinard Signed-off-by: Ralf Baechle