linux/include/asm-ia64/processor.h, branch v2.6.19

[IA64] Move perfmon tables from thread_struct to pfm_context

2006-09-26T19:03:13Z

This patch renders thread_struct->pmcs[] and thread_struct->pmds[] OBSOLETE. The actual table is moved to pfm_context structure which saves space in thread_struct (in turn saving space in task_struct which frees up more space for kernel stacks). Signed-off-by: Stephane Eranian Signed-off-by: Anil S Keshavamurthy Signed-off-by: Tony Luck

Pull model-name into release branch

2006-09-26T16:47:04Z

[IA64] Add "model name" to /proc/cpuinfo

2006-06-05T20:54:14Z

Linux ia64 port tried to decode the processor family number to something human-readable, but Intel brandnames don't change synchronously with updates to the family number. Adopt a more i386-like approach and just print the family number in decimal. Add a new field "model name" that uses PAL_BRAND_INFO to find the official name for the cpu, or on older systems, falls back to using the well-known codenames (Merced, McKinley, Madison). Signed-off-by: Tony Luck

Don't include linux/config.h from anywhere else in include/

2006-04-26T11:56:16Z

Signed-off-by: David Woodhouse

[IA64] add init declaration to cpu initialization functions

2006-03-23T00:04:37Z

Add init declaration to cpu initialization functions. Signed-off-by: Ken Chen Signed-off-by: Tony Luck

Pull sn2-mmio-writes into release branch

2006-03-21T16:21:26Z

Hand-fixed conflicts: include/asm-ia64/machvec_sn2.h Signed-off-by: Tony Luck

[IA64] avoid broken SAL_CACHE_FLUSH implementations

2006-02-02T21:25:54Z

If SAL_CACHE_FLUSH drops interrupts, complain about it and fall back to using PAL_CACHE_FLUSH instead. This is to work around a defect in HP rx5670 firmware: when an interrupt occurs during SAL_CACHE_FLUSH, SAL drops the interrupt but leaves it marked "in-service", which leaves the interrupt (and others of equal or lower priority) masked. Signed-off-by: Bjorn Helgaas Signed-off-by: Tony Luck

[IA64] hooks to wait for mmio writes to drain when migrating processes

2006-01-26T23:55:52Z

On SN2, MMIO writes which are issued from separate processors are not guaranteed to arrive in any particular order at the IO hardware. When performing such writes from the kernel this is not a problem, as a kernel thread will not migrate to another CPU during execution, and mmiowb() calls can guarantee write ordering when control of the IO resource is allowed to move between threads. However, when MMIO writes can be performed from user space (e.g. DRM) there are no such guarantees and mechanisms, as the process may context-switch at any time, and may migrate to a different CPU as part of the switch. For such programs/hardware to operate correctly, it is required that the MMIO writes from the old CPU be accepted by the IO hardware before subsequent writes from the new CPU can be issued. The following patch implements this behavior on SN2 by waiting for a Shub register to indicate that these writes have been accepted. This is placed in the context switch-in path, and only performs the wait when the newly scheduled task changes CPUs. Signed-off-by: Prarit Bhargava Signed-off-by: Brent Casavant

[IA64] Perfmon for Montecito

2006-01-16T18:31:44Z

Add Montecito PMU description table for perfmon2 Signed-off-by: Stephane Eranian Signed-off-by: Tony Luck

[PATCH] ia64: task_pt_regs()

2006-01-12T17:08:58Z

Signed-off-by: Al Viro Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds