<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl, branch v3.4.30</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/drivers/pinctrl?h=v3.4.30</id>
<link rel='self' href='https://git.amat.us/linux/atom/drivers/pinctrl?h=v3.4.30'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2012-10-28T17:14:14Z</updated>
<entry>
<title>pinctrl: tegra: set low power mode bank width to 2</title>
<updated>2012-10-28T17:14:14Z</updated>
<author>
<name>Pritesh Raithatha</name>
<email>praithatha@nvidia.com</email>
</author>
<published>2012-10-17T11:39:36Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=248ada294174583d918564de33bc5504311c69bb'/>
<id>urn:sha1:248ada294174583d918564de33bc5504311c69bb</id>
<content type='text'>
commit 154f3ebf53edcfbe28728452b4ab37a118581125 upstream.

Signed-off-by: Pritesh Raithatha &lt;praithatha@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>pinctrl: tegra: correct bank for pingroup and drv pingroup</title>
<updated>2012-10-28T17:14:14Z</updated>
<author>
<name>Pritesh Raithatha</name>
<email>praithatha@nvidia.com</email>
</author>
<published>2012-10-17T06:21:37Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=409dcaefb5c287d68c36e2598154b979a67a9447'/>
<id>urn:sha1:409dcaefb5c287d68c36e2598154b979a67a9447</id>
<content type='text'>
commit a03690e44468dcd3088f6600ab036d17bd2130ff upstream.

Signed-off-by: Pritesh Raithatha &lt;praithatha@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>pinctrl: implement pinctrl_check_ops</title>
<updated>2012-04-11T07:31:02Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@wwwdotorg.org</email>
</author>
<published>2012-03-16T20:54:25Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=f84cc342b1999db11ece939e1d2bf0743eb4578b'/>
<id>urn:sha1:f84cc342b1999db11ece939e1d2bf0743eb4578b</id>
<content type='text'>
Most code assumes that the pinctrl ops are present. Validate this when
registering a pinctrl driver. Remove the one place in the code that
was checking whether one of these non-optional ops was present.

Signed-off-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: support pinconfig on the U300</title>
<updated>2012-03-12T21:49:03Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2011-11-16T20:58:10Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5'/>
<id>urn:sha1:dc0b1aa3e2fefa6372f38d7f6d5d33581567a1b5</id>
<content type='text'>
This adds pin configuration support for the U300 driver pair,
we can now read out the biasing and drive mode in debugfs and
configure it using the new configuration API.

ChangeLog v1-&gt;v2:
- Migrate to pin config and generic pin config changes.
ChangeLog v2-&gt;v3:
- Adjust to generic pin config changes in v7 patch set.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl/coh901: use generic pinconf enums and parameters</title>
<updated>2012-03-12T21:49:02Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2011-11-16T19:10:09Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=a050b3eee61666421df786c8d898ec22c129f4af'/>
<id>urn:sha1:a050b3eee61666421df786c8d898ec22c129f4af</id>
<content type='text'>
Adjust the COH 901 driver to use the standard enums for
biasing and driving pins, alter signature of config function
to suit the framework.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: introduce generic pin config</title>
<updated>2012-03-12T21:49:02Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2011-11-24T17:27:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=394349f7789fdfcdc74b61afcac84046535c40b7'/>
<id>urn:sha1:394349f7789fdfcdc74b61afcac84046535c40b7</id>
<content type='text'>
This is a split-off from the earlier patch set which adds generic
pin configuration for the pin controllers that want it. Since
we may have a system with mixed generic and custom pin controllers,
we pass a boolean in the pin controller ops vtable to indicate
if it is generic.

ChangeLog v1-&gt;v5:
- Follow parent patch versioning number system.
- Document the semantic meaning of return values from pin config
  get functions, so we can iterate over pins and check their
  properties from debugfs as part of the generic config code.
- Use proper cast functions in the generic debugfs pin config
  file.
- Expand generic config to optionally cover groups too.
ChangeLog v5-&gt;v6:
- Update to match underlying changes.
ChangeLog v6-&gt;v7:
- Drop DRIVE_OFF parameter, use bias high impedance for this
- Delete argument for drive modes push-pull, od and os. These
  are now just state transitions.
- Delete slew rate rising/falling due to discussions on on
  proper semantics
- Drop config wakeup, struct irq_chip does this for now, add
  back if need be.
- Set PIN_CONFIG_END to 0x7fff making room for custom config
  parameters from 0x8000 and up.
- Prefix accessor functions with pinconf_
</content>
</entry>
<entry>
<title>pinctrl: fix error path in pinconf_map_to_setting()</title>
<updated>2012-03-12T21:48:43Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2012-03-12T20:38:29Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=70b36378d44d7f5e62458a830b1a9bb1c570f28a'/>
<id>urn:sha1:70b36378d44d7f5e62458a830b1a9bb1c570f28a</id>
<content type='text'>
The code was using the union member
setting-&gt;data.configs.group_or_pin to store a potential
error code, but since that member is unsigned the
&lt; 0 comparison was not true, letting errors pass through,
ending up as mapped to pin "-22". Fix this up and print
the error.

Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: allow concurrent gpio and mux function ownership of pins</title>
<updated>2012-03-12T21:43:09Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-03-06T00:22:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=652162d469a73450a66b6c8049b16c2b7828fa24'/>
<id>urn:sha1:652162d469a73450a66b6c8049b16c2b7828fa24</id>
<content type='text'>
Per recent updates to Documentation/gpio.txt, gpiolib drivers should
inform pinctrl when a GPIO is requested. pinctrl then marks that pin as
in-use for that GPIO function.

When an SoC muxes pins in a group, it's quite possible for the group to
contain e.g. 6 pins, but only 4 of them actually be needed by the HW
module that's mux'd to them. In this case, the other 2 pins could be
used as GPIOs. However, pinctrl marks all the pins within the group as
in-use by the selected mux function. To allow the expected gpiolib
interaction, separate the concepts of pin ownership into two parts: One
for the mux function and one for GPIO usage. Finally, allow those two
ownerships to exist in parallel.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pinctrl-tegra-for-next-diet' into for-next</title>
<updated>2012-03-06T22:30:15Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2012-03-06T22:30:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=a6c3b33f02c799db69a3cd82545e45e9df3d69ca'/>
<id>urn:sha1:a6c3b33f02c799db69a3cd82545e45e9df3d69ca</id>
<content type='text'>
</content>
</entry>
<entry>
<title>pinctrl: include machine header to core.h</title>
<updated>2012-03-06T22:07:41Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2012-03-06T12:52:22Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=872acc322c74bb06b7ceb61fe93314e2da32362c'/>
<id>urn:sha1:872acc322c74bb06b7ceb61fe93314e2da32362c</id>
<content type='text'>
struct pinctrl_setting contains an enum pinctrl_map_type
field, so we need to include machine.h. Also fix kerneldoc
to indicate that the pinctrl_setting is about both muxing
and other config.

Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
