<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/ntb, branch v3.12.10</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/drivers/ntb?h=v3.12.10</id>
<link rel='self' href='https://git.amat.us/linux/atom/drivers/ntb?h=v3.12.10'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2013-09-05T18:08:01Z</updated>
<entry>
<title>ntb: clean up unnecessary MSI/MSI-X capability find</title>
<updated>2013-09-05T18:08:01Z</updated>
<author>
<name>Yijing Wang</name>
<email>wangyijing@huawei.com</email>
</author>
<published>2013-08-08T13:09:34Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=73f47cadfe29f98c48d7fbac4dd79d3e7979ee0b'/>
<id>urn:sha1:73f47cadfe29f98c48d7fbac4dd79d3e7979ee0b</id>
<content type='text'>
PCI core will initialize device MSI/MSI-X capability in
pci_msi_init_pci_dev(). So device driver should use
pci_dev-&gt;msi_cap/msix_cap to determine whether the device
support MSI/MSI-X instead of using
pci_find_capability(pci_dev, PCI_CAP_ID_MSI/MSIX).
Access to PCIe device config space again will consume more time.

Signed-off-by: Yijing Wang &lt;wangyijing@huawei.com&gt;
Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Update Version</title>
<updated>2013-09-05T18:08:00Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-07-30T22:44:05Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=db3bb3f07eac9c83c866313c5f54bc80c3b860e5'/>
<id>urn:sha1:db3bb3f07eac9c83c866313c5f54bc80c3b860e5</id>
<content type='text'>
Update NTB version to 1.0

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Comment Fix</title>
<updated>2013-09-05T18:08:00Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-07-29T23:46:43Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=f9a2cf890b8e6c0a4ce510593f6f3c58394dbcae'/>
<id>urn:sha1:f9a2cf890b8e6c0a4ce510593f6f3c58394dbcae</id>
<content type='text'>
Add "data" ntb_register_db_callback parameter description comment and
correct poor spelling.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Remove unused variable</title>
<updated>2013-09-05T18:07:59Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-09-03T21:38:19Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=3daa3a073e8813e4185d614f2c6b601ce39e2e5f'/>
<id>urn:sha1:3daa3a073e8813e4185d614f2c6b601ce39e2e5f</id>
<content type='text'>
Remove unused pci_dev variable from ntb_transport_free()

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Remove References of non-B2B BWD HW</title>
<updated>2013-09-05T18:07:59Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-07-15T22:33:18Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=b1ef004303fba92cd28ed32dd3caed3438238f76'/>
<id>urn:sha1:b1ef004303fba92cd28ed32dd3caed3438238f76</id>
<content type='text'>
NTB-RP is not a supported configuration on BWD hardware.  Remove the
code attempting to set it up.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: NTB-RP support</title>
<updated>2013-09-05T18:07:58Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-07-15T23:43:54Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=ed6c24eda97b6bdcd013dbd91cc5c8b02de507e9'/>
<id>urn:sha1:ed6c24eda97b6bdcd013dbd91cc5c8b02de507e9</id>
<content type='text'>
Add support for Non-Transparent Bridge connected to a PCI-E Root Port on
the remote system (also known as NTB-RP mode).  This allows for a NTB
enabled system to be connected to a non-NTB enabled system/slot.

Modifications to the registers and BARs/MWs on the Secondary side by the
remote system are reflected into registers on the Primary side for the
local system.  Similarly, modifications of registers and BARs/MWs on
Primary side by the local system are reflected into registers on the
Secondary side for the Remote System.  This allows communication between
the 2 sides via these registers and BARs/MWs.

Note: there is not a fix for the Xeon Errata (that was already worked
around in NTB-B2B mode) for NTB-RP mode.  Due to this limitation, NTB-RP
will not work on the Secondary side with the Xeon Errata workaround
enabled.  To get around this, disable the workaround via the
xeon_errata_workaround=0 modparm.  However, this can cause the hang
described in the errata.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Rename Variables for NTB-RP</title>
<updated>2013-09-05T18:07:58Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-07-15T22:53:54Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=497938890a0121d040683aa1db42cad8daf7ae97'/>
<id>urn:sha1:497938890a0121d040683aa1db42cad8daf7ae97</id>
<content type='text'>
Many variable names in the NTB driver refer to the primary or secondary
side.  However, these variables will be used to access the reverse case
when in NTB-RP mode.  Make these names more generic in anticipation of
NTB-RP support.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Use DMA Engine to Transmit and Receive</title>
<updated>2013-09-05T18:04:09Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-02-12T16:52:50Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=282a2feeb9bfb1d1dfbad93df206b74eaf80d564'/>
<id>urn:sha1:282a2feeb9bfb1d1dfbad93df206b74eaf80d564</id>
<content type='text'>
Allocate and use a DMA engine channel to transmit and receive data over
NTB.  If none is allocated, fall back to using the CPU to transfer data.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
Reviewed-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Reviewed-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Enable 32bit Support</title>
<updated>2013-09-03T21:48:53Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2013-01-21T23:40:39Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=ac477afb0431386575ef453f50fa0052c3f0461b'/>
<id>urn:sha1:ac477afb0431386575ef453f50fa0052c3f0461b</id>
<content type='text'>
Correct the issues on NTB that prevented it from working on x86_32 and
modify the Kconfig to allow it to be permitted to be used in that
environment as well.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
<entry>
<title>NTB: Update Device IDs</title>
<updated>2013-09-03T21:48:53Z</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2012-09-28T18:38:48Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=be4dac0fcacd7d62e0b4f7ff51a7032e197b62af'/>
<id>urn:sha1:be4dac0fcacd7d62e0b4f7ff51a7032e197b62af</id>
<content type='text'>
Add support for new Intel NTB devices on upcoming Xeon hardware.  Since
the Xeon hardware design is already in place in the driver, all that is
needed are the new device ids.

Remove the device IDs for NTB devs running in Transparent Bridge mode,
as this driver is not being used for those devices.

Rename the device IDs for NTB devs running in NTB-RP mode to better
identify their usage model.  "PS" to denote the Primary Side of NTB, and
"SS" to denote the secondary side.  The primary side is the interface
exposed to the local system, and the secondary side is the interface
exposed to the remote system.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
</entry>
</feed>
