<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/i2c, branch v3.4.81</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/drivers/i2c?h=v3.4.81</id>
<link rel='self' href='https://git.amat.us/linux/atom/drivers/i2c?h=v3.4.81'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2013-12-12T06:34:11Z</updated>
<entry>
<title>i2c: i801: SMBus patch for Intel Avoton DeviceIDs</title>
<updated>2013-12-12T06:34:11Z</updated>
<author>
<name>Seth Heasley</name>
<email>seth.heasley@intel.com</email>
</author>
<published>2013-01-30T15:25:32Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=3e80f4c2247595e2901f5ef262a524276cfb1d28'/>
<id>urn:sha1:3e80f4c2247595e2901f5ef262a524276cfb1d28</id>
<content type='text'>
commit c2db409cbc8751ccc7e6d2cc2e41af0d12ea637f upstream.

This patch adds the PCU SMBus DeviceID for the Intel Avoton SOC.

Signed-off-by: Seth Heasley &lt;seth.heasley@intel.com&gt;
Reviewed-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Wolfram Sang &lt;w.sang@pengutronix.de&gt;
Cc: "Ong, Boon Leong" &lt;boon.leong.ong@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>i2c: designware: always clear interrupts before enabling them</title>
<updated>2013-05-24T18:14:22Z</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2013-05-13T00:54:30Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=1cd75cf191d5e3995e22d7bfc573939ffeebcc51'/>
<id>urn:sha1:1cd75cf191d5e3995e22d7bfc573939ffeebcc51</id>
<content type='text'>
commit 2a2d95e9d6d29e726cc294b65391917ed2e32bf4 upstream.

If the I2C bus is put to a low power state by an ACPI method it might pull
the SDA line low (as its power is removed). Once the bus is put to full
power state again, the SDA line is pulled back to high. This transition
looks like a STOP condition from the controller point-of-view which sets
STOP detected bit in its status register causing the driver to fail
subsequent transfers.

Fix this by always clearing all interrupts before we start a transfer.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Wolfram Sang &lt;wsa@the-dreams.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>i2c: xiic: must always write 16-bit words to TX_FIFO</title>
<updated>2013-05-08T02:51:54Z</updated>
<author>
<name>Steven A. Falco</name>
<email>sfalco@harris.com</email>
</author>
<published>2013-04-22T09:34:39Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=0e079960ed813d36aa7625da4c388ae0d6e9d320'/>
<id>urn:sha1:0e079960ed813d36aa7625da4c388ae0d6e9d320</id>
<content type='text'>
commit c39e8e4354ce4daf23336de5daa28a3b01f00aa6 upstream.

The TX_FIFO register is 10 bits wide.  The lower 8 bits are the data to be
written, while the upper two bits are flags to indicate stop/start.

The driver apparently attempted to optimize write access, by only writing a
byte in those cases where the stop/start bits are zero.  However, we have
seen cases where the lower byte is duplicated onto the upper byte by the
hardware, which causes inadvertent stop/starts.

This patch changes the write access to the transmit FIFO to always be 16 bits
wide.

Signed off by: Steven A. Falco &lt;sfalco@harris.com&gt;
Signed-off-by: Wolfram Sang &lt;wsa@the-dreams.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>i2c-i801: Add Device IDs for Intel Lynx Point-LP PCH</title>
<updated>2012-09-14T17:00:33Z</updated>
<author>
<name>James Ralston</name>
<email>james.d.ralston@intel.com</email>
</author>
<published>2012-09-10T08:14:02Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=7db3f56f37640c88387dfda6fad1e930d589d0e3'/>
<id>urn:sha1:7db3f56f37640c88387dfda6fad1e930d589d0e3</id>
<content type='text'>
commit 4a8f1ddde942e232387e6129ce4f4c412e43802f upstream.

Add the SMBus Device IDs for the Intel Lynx Point-LP PCH.

Signed-off-by: James Ralston &lt;james.d.ralston@intel.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>i2c-designware: Fix build error if CONFIG_I2C_DESIGNWARE_PLATFORM=y &amp;&amp; CONFIG_I2C_DESIGNWARE_PCI=y</title>
<updated>2012-09-14T17:00:32Z</updated>
<author>
<name>Axel Lin</name>
<email>axel.lin@gmail.com</email>
</author>
<published>2012-09-10T08:14:02Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=f313f5b440c874dbee75922e30736b9069f0a1d1'/>
<id>urn:sha1:f313f5b440c874dbee75922e30736b9069f0a1d1</id>
<content type='text'>
commit e68bb91baa0bb9817567bd45d560919e8e26373b upstream.

This patch adds config I2C_DESIGNWARE_CORE in Kconfig, and let
I2C_DESIGNWARE_PLATFORM and I2C_DESIGNWARE_PCI select I2C_DESIGNWARE_CORE.

Because both I2C_DESIGNWARE_PLATFORM and I2C_DESIGNWARE_PCI can be built as
built-in or module, we also need to export the functions in i2c-designware-core.

This fixes below build error when CONFIG_I2C_DESIGNWARE_PLATFORM=y &amp;&amp;
CONFIG_I2C_DESIGNWARE_PCI=y:

  LD      drivers/i2c/busses/built-in.o
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_clear_int':
i2c-designware-core.c:(.text+0xa10): multiple definition of `i2c_dw_clear_int'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x928): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_init':
i2c-designware-core.c:(.text+0x178): multiple definition of `i2c_dw_init'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x90): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `dw_readl':
i2c-designware-core.c:(.text+0xe8): multiple definition of `dw_readl'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x0): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_isr':
i2c-designware-core.c:(.text+0x724): multiple definition of `i2c_dw_isr'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x63c): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_xfer':
i2c-designware-core.c:(.text+0x4b0): multiple definition of `i2c_dw_xfer'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x3c8): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_is_enabled':
i2c-designware-core.c:(.text+0x9d4): multiple definition of `i2c_dw_is_enabled'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x8ec): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `dw_writel':
i2c-designware-core.c:(.text+0x124): multiple definition of `dw_writel'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x3c): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_xfer_msg':
i2c-designware-core.c:(.text+0x2e8): multiple definition of `i2c_dw_xfer_msg'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x200): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_enable':
i2c-designware-core.c:(.text+0x9c8): multiple definition of `i2c_dw_enable'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x8e0): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_read_comp_param':
i2c-designware-core.c:(.text+0xa24): multiple definition of `i2c_dw_read_comp_param'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x93c): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_disable':
i2c-designware-core.c:(.text+0x9dc): multiple definition of `i2c_dw_disable'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x8f4): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_func':
i2c-designware-core.c:(.text+0x710): multiple definition of `i2c_dw_func'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x628): first defined here
drivers/i2c/busses/i2c-designware-pci.o: In function `i2c_dw_disable_int':
i2c-designware-core.c:(.text+0xa18): multiple definition of `i2c_dw_disable_int'
drivers/i2c/busses/i2c-designware-platform.o:i2c-designware-platdrv.c:(.text+0x930): first defined here
make[3]: *** [drivers/i2c/busses/built-in.o] Error 1
make[2]: *** [drivers/i2c/busses] Error 2
make[1]: *** [drivers/i2c] Error 2
make: *** [drivers] Error 2

Signed-off-by: Axel Lin &lt;axel.lin@gmail.com&gt;
Signed-off-by: Jean Delvare &lt;khali@linux-fr.org&gt;
Tested-by: Jiri Slaby &lt;jslaby@suse.cz&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>i2c: tegra: notify transfer-complete after clearing status.</title>
<updated>2012-06-01T07:18:28Z</updated>
<author>
<name>Laxman Dewangan</name>
<email>ldewangan@nvidia.com</email>
</author>
<published>2012-05-07T06:46:19Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=3e5f29bd22e597d66d9c1013a0ab190e6b48a8ba'/>
<id>urn:sha1:3e5f29bd22e597d66d9c1013a0ab190e6b48a8ba</id>
<content type='text'>
commit c889e91d2cc22123f20f40dde0c0a91856a20eea upstream.

The notification of the transfer complete by calling complete()
should be done after clearing all interrupt status.
This avoids the race condition of misconfigure the i2c controller
in multi-core environment.

Signed-off-by: Laxman Dewangan &lt;ldewangan@nvidia.com&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Signed-off-by: Wolfram Sang &lt;w.sang@pengutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>i2c: davinci: Free requested IRQ in remove</title>
<updated>2012-06-01T07:18:28Z</updated>
<author>
<name>Marcus Folkesson</name>
<email>marcus.folkesson@gmail.com</email>
</author>
<published>2012-05-03T13:56:36Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=16d815fd230b81d49d395e91b084f0731ea6e4a2'/>
<id>urn:sha1:16d815fd230b81d49d395e91b084f0731ea6e4a2</id>
<content type='text'>
commit 9868a060ccf769c08ec378a9829137e272e9a92c upstream.

The freed IRQ is not necessary the one requested in probe.
Even if it was, with two or more i2c-controllers it will fails anyway.

Signed-off-by: Marcus Folkesson &lt;marcus.folkesson@gmail.com&gt;
Signed-off-by: Wolfram Sang &lt;w.sang@pengutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>i2c: mxs: disable QUEUE when sending is done</title>
<updated>2012-04-27T14:13:29Z</updated>
<author>
<name>Wolfram Sang</name>
<email>w.sang@pengutronix.de</email>
</author>
<published>2012-04-25T11:39:38Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=1e4f0b82577e59f23484c99056c96465e202fdd5'/>
<id>urn:sha1:1e4f0b82577e59f23484c99056c96465e202fdd5</id>
<content type='text'>
Since the last fixes to this driver ensure now the queue termination is
done correctly, we can finally disable the queue after a transfer
without problems. The gain is that it will only be reenabled after the
next transfer is fully set up. Before, the queue was running all the
time and if the setup of the next message was interrupted by another
thread, an incomplete buffer could have been sent, padded with zeroes.

Signed-off-by: Wolfram Sang &lt;w.sang@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>i2c: mxs: handle spurious interrupt</title>
<updated>2012-04-25T20:59:44Z</updated>
<author>
<name>Wolfram Sang</name>
<email>w.sang@pengutronix.de</email>
</author>
<published>2012-04-05T14:15:24Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=c95eeae9e39314273bcda057f27100603d333518'/>
<id>urn:sha1:c95eeae9e39314273bcda057f27100603d333518</id>
<content type='text'>
After an error interrupt setting cmd-&gt;err, I see another interrupt that
the data engine is empty which clears cmd-&gt;err before being processed.
So, clear cmd-&gt;err at the beginning of a transfer only to handle these
consecutive interrupts.

Signed-off-by: Wolfram Sang &lt;w.sang@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>i2c-eg20t: Modify MODULE_AUTHOR's email address</title>
<updated>2012-04-22T19:29:06Z</updated>
<author>
<name>Tomoya MORINAGA</name>
<email>tomoya.rohm@gmail.com</email>
</author>
<published>2012-03-26T05:55:23Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=096407136769ec10690abe1baba092abcb763662'/>
<id>urn:sha1:096407136769ec10690abe1baba092abcb763662</id>
<content type='text'>
Signed-off-by: Tomoya MORINAGA &lt;tomoya.rohm@gmail.com&gt;
Signed-off-by: Wolfram Sang &lt;w.sang@pengutronix.de&gt;
</content>
</entry>
</feed>
