linux/drivers/gpu, branch v3.4

drm/nouveau/i2c: resume use of i2c-algo-bit, rather than custom stack

2012-05-07T10:02:38Z

Previous issues with i2c-algo-bit have now been resolved. This is a revert of f553b79c03f0dbd52f6f03abe8233a2bef8cbd0d mostly, due to fixes in the i2c core repairing the original issue, this code isn't required and was causing regressions. Signed-off-by: Ben Skeggs Reported-by: Nick Bowler Tested-by: Nick Bowler Signed-off-by: Dave Airlie

drm/i915: Do no set Stencil Cache eviction LRA w/a on gen7+

2012-05-07T08:37:56Z

I've flagged this while reviewing the first version and Ken Graunke fixed it up in v2, but unfortunately Dave Airlie picked up the wrong version. Cc: Dave Airlie Cc: Kenneth Graunke Cc: stable@kernel.org Signed-Off-by: Daniel Vetter

drm/i915: disable sdvo hotplug on i945g/gm

2012-05-07T08:37:56Z

Chris Wilson dug out a hw erratum saying that there's noise on the interrupt line on i945G chips. We also have a bug report from a i945GM chip with an sdvo hotplug interrupt storm (and no apparent cause). Play it safe and disable sdvo hotplug on all i945 variants. Note that this is a regression that has been introduced in 3.1, when we've enabled sdvo hotplug support with commit cc68c81aed7d892deaf12d720d5455208e94cd0a Author: Simon Farnsworth Date: Wed Sep 21 17:13:30 2011 +0100 drm/i915: Enable SDVO hotplug interrupts for HDMI and DVI Cc: stable@kernel.org Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=38442 Reported-and-tested-by: Dominik Köppl Reviewed-by: Chris Wilson Signed-Off-by: Daniel Vetter

drm/radeon: clarify and extend wb setup on APUs and NI+ asics

2012-05-04T08:36:11Z

Use family rather than DCE check for clarity, also always use wb on APUs, there will never be AGP variants. Signed-off-by: Alex Deucher Reviewed-by: Michel Dänzer Signed-off-by: Dave Airlie

Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes

2012-05-03T16:27:02Z

* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: enable dip before writing data on gen4 fixing dmi match for hp t5745 and hp st5747 thin client drm/i915: Only enable IPS polling for gen5 drm/i915: Do not read non-existent DPLL registers on PCH hardware

drm/i915: enable dip before writing data on gen4

2012-05-03T13:55:38Z

While testing with the intel_infoframes tool on gen4, I see that when video DIP is disabled, what we write to the DATA memory is not exactly what we read back later. This regression has been introduce in commit 64a8fc0145a1d0fdc25fc9367c2e6c621955fb3b Author: Jesse Barnes Date: Thu Sep 22 11:16:00 2011 +0530 drm/i915: fix ILK+ infoframe support That commit was setting VIDEO_DIP_CTL to 0 when initializing, which caused the problem. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43947 Cc: stable@kernel.org Tested-by: Yang Guang Signed-off-by: Paulo Zanoni Reviewed-by: Eugeni Dodonov [danvet: Pimped commit message by using the usual commit citation layout.] Signed-off-by: Daniel Vetter

nouveau: initialise has_optimus variable.

2012-05-03T08:30:58Z

We should initialise this to 0 really to avoid getting false positives. Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie

fixing dmi match for hp t5745 and hp st5747 thin client

2012-05-02T19:41:33Z

Match the correct information which is DMI_PRODUCT_NAME instead of DMI_BOARD_NAME See dmidecode information on launchpad for both thin client: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/911920 https://bugs.launchpad.net/ubuntu/+source/linux/+bug/911916 Signed-off-by: Marc Gariepy Reviewed-by: Adam Jackson Signed-Off-by: Daniel Vetter

drm/i915: Only enable IPS polling for gen5

2012-05-02T12:37:52Z

On SandyBridge IPS was entirely implemented in hardware and not reliant on the driver monitoring power consumption and feeding back desired run states, so the hardware is able to adapt quicker and more flexibly. Which is a huge relief for us as we no longer have to carry empirically derived magic algorithms. Yet despite the advance in technology, the driver was still doing its IPS polling on all machines. Restrict it to the only supported hardware, Clarkdale/Arrandale. Signed-off-by: Chris Wilson Reviewed-by: Jesse Barnes Tested-by: Andrey Rahmatullin Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49025 Signed-off-by: Daniel Vetter

drm/i915: Do not read non-existent DPLL registers on PCH hardware

2012-05-02T12:37:51Z

We only execute intel_decrease_pllclock for pre-PCH hardware, typically gen4 mobiles. However, in the variable declaration we did read from the non-PCH DPLL register, quite naughty and detected by SandyBridge. Reported-and-tested-by: Andrey Rahmatullin Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49025 Signed-off-by: Chris Wilson Signed-Off-by: Daniel Vetter