<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/dma, branch v2.6.38.4</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/drivers/dma?h=v2.6.38.4</id>
<link rel='self' href='https://git.amat.us/linux/atom/drivers/dma?h=v2.6.38.4'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2011-02-14T10:40:46Z</updated>
<entry>
<title>Merge branch 'imx' into dmaengine-fixes</title>
<updated>2011-02-14T10:40:46Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2011-02-14T10:40:46Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=e19d1d4988f8020c25bf1758f9a898e1374cef35'/>
<id>urn:sha1:e19d1d4988f8020c25bf1758f9a898e1374cef35</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dma: ipu_idmac: do not lose valid received data in the irq handler</title>
<updated>2011-02-14T10:28:16Z</updated>
<author>
<name>Anatolij Gustschin</name>
<email>agust@denx.de</email>
</author>
<published>2011-01-31T12:22:29Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=a646bd7f0824d3e0f02ff8d7410704f965de01bc'/>
<id>urn:sha1:a646bd7f0824d3e0f02ff8d7410704f965de01bc</id>
<content type='text'>
Currently when two or more buffers are queued by the camera driver
and so the double buffering is enabled in the idmac, we lose one
frame comming from CSI since the reporting of arrival of the first
frame is deferred by the DMAIC_7_EOF interrupt handler and reporting
of the arrival of the last frame is not done at all. So when requesting
N frames from the image sensor we actually receive N - 1 frames in
user space.

The reason for this behaviour is that the DMAIC_7_EOF interrupt
handler misleadingly assumes that the CUR_BUF flag is pointing to the
buffer used by the IDMAC. Actually it is not the case since the
CUR_BUF flag will be flipped by the FSU when the FSU is sending the
&lt;TASK&gt;_NEW_FRM_RDY signal when new frame data is delivered by the CSI.
When sending this singal, FSU updates the DMA_CUR_BUF and the
DMA_BUFx_RDY flags: the DMA_CUR_BUF is flipped, the DMA_BUFx_RDY
is cleared, indicating that the frame data is beeing written by
the IDMAC to the pointed buffer. DMA_BUFx_RDY is supposed to be
set to the ready state again by the MCU, when it has handled the
received data. DMAIC_7_CUR_BUF flag won't be flipped here by the
IPU, so waiting for this event in the EOF interrupt handler is wrong.
Actually there is no spurious interrupt as described in the comments,
this is the valid DMAIC_7_EOF interrupt indicating reception of the
frame from CSI.

The patch removes code that waits for flipping of the DMAIC_7_CUR_BUF
flag in the DMAIC_7_EOF interrupt handler. As the comment in the
current code denotes, this waiting doesn't help anyway. As a result
of this removal the reporting of the first arrived frame is not
deferred to the time of arrival of the next frame and the drivers
software flag 'ichan-&gt;active_buffer' is in sync with DMAIC_7_CUR_BUF
flag, so the reception of all requested frames works.

This has been verified on the hardware which is triggering the
image sensor by the programmable state machine, allowing to
obtain exact number of frames. On this hardware we do not tolerate
losing frames.

This patch also removes resetting the DMA_BUFx_RDY flags of
all channels in ipu_disable_channel() since transfers on other
DMA channels might be triggered by other running tasks and the
buffers should always be ready for data sending or reception.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Reviewed-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Tested-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'dmaengine-shawn' into dmaengine</title>
<updated>2011-01-31T11:42:51Z</updated>
<author>
<name>Sascha Hauer</name>
<email>s.hauer@pengutronix.de</email>
</author>
<published>2011-01-31T11:42:51Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=60f1df5dc6ecd07befc332ae30109fb86505634c'/>
<id>urn:sha1:60f1df5dc6ecd07befc332ae30109fb86505634c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge branch 'dmaengine-sdma' into dmaengine</title>
<updated>2011-01-31T11:42:48Z</updated>
<author>
<name>Sascha Hauer</name>
<email>s.hauer@pengutronix.de</email>
</author>
<published>2011-01-31T11:42:48Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=2335d338a20a6f5ac70ae4338733c8ff5933f978'/>
<id>urn:sha1:2335d338a20a6f5ac70ae4338733c8ff5933f978</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dmaengine: imx-sdma: fix up param for the last BD in sdma_prep_slave_sg()</title>
<updated>2011-01-31T11:42:23Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@freescale.com</email>
</author>
<published>2011-01-19T21:50:39Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=341b9419a8c0a4cdb75773c576870f1eb655516d'/>
<id>urn:sha1:341b9419a8c0a4cdb75773c576870f1eb655516d</id>
<content type='text'>
As per the reference manual, bit "L" should be set while bit "C"
should be cleared for the last buffer descriptor in the non-cyclic
chain, so that sdma can stop trying to find the next BD and end
the transfer.

In case of sdma_prep_slave_sg(), BD_LAST needs to be set and BD_CONT
be cleared for the last BD.

Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>dmaengine: imx-sdma: correct sdmac-&gt;status in sdma_handle_channel_loop()</title>
<updated>2011-01-31T11:42:12Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@freescale.com</email>
</author>
<published>2011-01-19T21:50:38Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=1e9cebb42de57f1243261939c77ab5b0f9bcf311'/>
<id>urn:sha1:1e9cebb42de57f1243261939c77ab5b0f9bcf311</id>
<content type='text'>
sdma_handle_channel_loop() is the handler of cyclic tx.  One period
success does not really mean the success of the tx.  Instead of
DMA_SUCCESS, DMA_IN_PROGRESS should be the one to tell.

Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>dmaengine: imx-sdma: return sdmac-&gt;status in sdma_tx_status()</title>
<updated>2011-01-31T11:41:59Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@freescale.com</email>
</author>
<published>2011-01-19T21:50:37Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=8a9659114c7be6f88253618252881ea6fe0588b4'/>
<id>urn:sha1:8a9659114c7be6f88253618252881ea6fe0588b4</id>
<content type='text'>
The sdmac-&gt;status was designed to reflect the status of the tx,
so simply return it in sdma_tx_status().  Then dma client can call
dma_async_is_tx_complete() to know the status of the tx.

Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>dmaengine: imx-sdma: set sdmac-&gt;status to DMA_ERROR in err_out of sdma_prep_slave_sg()</title>
<updated>2011-01-31T11:41:50Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@freescale.com</email>
</author>
<published>2011-01-19T21:50:36Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=4b2ce9ddb370c4eb573540611c347d78ac4b54a0'/>
<id>urn:sha1:4b2ce9ddb370c4eb573540611c347d78ac4b54a0</id>
<content type='text'>
sdma_prep_dma_cyclic() sets sdmac-&gt;status to DMA_ERROR in err_out,
and sdma_prep_slave_sg() needs to do the same.  Otherwise,
sdmac-&gt;status stays at DMA_IN_PROGRESS, which will make the function
return immediately next time it gets called.

Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>dmaengine: imx-sdma: remove IMX_DMA_SG_LOOP handling in sdma_prep_slave_sg()</title>
<updated>2011-01-31T11:41:43Z</updated>
<author>
<name>Shawn Guo</name>
<email>shawn.guo@freescale.com</email>
</author>
<published>2011-01-19T21:50:35Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=1797c33f0edcdcc9a483c06233a203786666a97f'/>
<id>urn:sha1:1797c33f0edcdcc9a483c06233a203786666a97f</id>
<content type='text'>
This is a leftover from the time that the driver did not have
sdma_prep_dma_cyclic callback and implemented sound dma as a looped
sg chain.  And it can be removed now.

Signed-off-by: Shawn Guo &lt;shawn.guo@freescale.com&gt;
Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>dmaengine i.MX dma: initialize dma capabilities outside channel loop</title>
<updated>2011-01-31T11:36:23Z</updated>
<author>
<name>Sascha Hauer</name>
<email>s.hauer@pengutronix.de</email>
</author>
<published>2011-01-31T10:35:59Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=f8a356ff96a9070156f863e4f7716e2a0eb8c995'/>
<id>urn:sha1:f8a356ff96a9070156f863e4f7716e2a0eb8c995</id>
<content type='text'>
The capabilities are device specific fields, not channel specific fields.

Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
</content>
</entry>
</feed>
