<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/dma, branch mybooklive</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/drivers/dma?h=mybooklive</id>
<link rel='self' href='https://git.amat.us/linux/atom/drivers/dma?h=mybooklive'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2014-08-13T23:11:53Z</updated>
<entry>
<title>gpl-source-mybooklive-020202.zip</title>
<updated>2014-08-13T23:11:53Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T23:11:53Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=3918522a523adc3f001cf9c5da327d8fb383c26e'/>
<id>urn:sha1:3918522a523adc3f001cf9c5da327d8fb383c26e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gpl-source-mybooklive-020035.zip</title>
<updated>2014-08-13T23:04:11Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T23:04:11Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=f05c100b6a7051106229cda5a845e94e36e71b17'/>
<id>urn:sha1:f05c100b6a7051106229cda5a845e94e36e71b17</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gpl-source-mybooklive-010002-update.zip</title>
<updated>2014-08-13T21:14:13Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T21:14:13Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=ace6c6d243016e272050787c14e27a83ecd94a25'/>
<id>urn:sha1:ace6c6d243016e272050787c14e27a83ecd94a25</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ioat: fix infinite timeout checking in ioat2_quiesce</title>
<updated>2010-02-23T15:37:49Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2010-01-13T20:33:12Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=27df9c09dd64b05f862d5a05cfb1b1e479a44f0c'/>
<id>urn:sha1:27df9c09dd64b05f862d5a05cfb1b1e479a44f0c</id>
<content type='text'>
commit 7e55a70c5b9a57c12f49c44b0847c9343d4f54e4 upstream.

Fix typo in ioat2_quiesce. check 'tmo' is zero, not 'end'.  Also applies
to 2.6.32.3

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>ioat2,3: put channel hardware in known state at init</title>
<updated>2010-01-06T23:03:59Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2009-12-19T22:36:02Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=8b9f03819c4165799c463b14a30b23f228d13cdb'/>
<id>urn:sha1:8b9f03819c4165799c463b14a30b23f228d13cdb</id>
<content type='text'>
commit a6d52d70677e99bdb89b6921c265d0a58c22e597 upstream.

Put the ioat2 and ioat3 state machines in the halted state with all
errors cleared.

The ioat1 init path is not disturbed for stability, there are no
reported ioat1 initiaization issues.

Reported-by: Roland Dreier &lt;rdreier@cisco.com&gt;
Tested-by: Roland Dreier &lt;rdreier@cisco.com&gt;
Acked-by: Simon Horman &lt;horms@verge.net.au&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>ioat3: fix p-disabled q-continuation</title>
<updated>2010-01-06T23:03:58Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2009-12-17T20:52:39Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=e05a6f0307a79b77319eed3c892a9c09613f1a28'/>
<id>urn:sha1:e05a6f0307a79b77319eed3c892a9c09613f1a28</id>
<content type='text'>
commit cd78809f6191485a90ea6c92c2b58900ab5c156f upstream.

When continuing a pq calculation the driver needs 3 extra sources.  The
driver can perform a 3 source calculation with a single descriptor, but
needs an extended descriptor to process up to 8 sources in one
operation.  However, in the p-disabled case only one extra source is
needed.  When continuing a p-disabled operation there are occasions
(i.e. 0 &lt; src_cnt % 8 &lt; 3) where the tail operation does not need an
extended descriptor.  Properly account for this fact otherwise invalid
'dmacount' values will be written to hardware usually causing the
channel to halt with 'invalid descriptor' errors.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>dma: at_hdmac: correct incompatible type for argument 1 of 'spin_lock_bh'</title>
<updated>2010-01-06T23:03:51Z</updated>
<author>
<name>Nicolas Ferre</name>
<email>nicolas.ferre@atmel.com</email>
</author>
<published>2009-12-16T15:28:03Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=c4ddbba638a74b9110801026517e892e5a8db6ad'/>
<id>urn:sha1:c4ddbba638a74b9110801026517e892e5a8db6ad</id>
<content type='text'>
commit 4297a462f455e38f08976df7b16c849614a287da upstream.

Correct a typo error in locking calls.

Signed-off-by: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>shdma: fix initialization error handling</title>
<updated>2009-11-22T19:10:10Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2009-11-22T19:10:10Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=56adf7e8127d601b172e180b44551ce83404348f'/>
<id>urn:sha1:56adf7e8127d601b172e180b44551ce83404348f</id>
<content type='text'>
1/ Error handling code following a kzalloc should free the allocated data.
2/ Report an error when no platform data is detected

Both problems fixed by moving the platform data check before the allocation,
and allows a goto to be killed.

Reported-by: Julia Lawall &lt;julia@diku.dk&gt;
Acked-by: Julia Lawall &lt;julia@diku.dk&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>ioat3: fix pq completion versus channel deallocation race</title>
<updated>2009-11-20T06:21:03Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2009-11-20T00:11:03Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=49954c1567cb0d70d28bb5512d471dc5bd4e2c3f'/>
<id>urn:sha1:49954c1567cb0d70d28bb5512d471dc5bd4e2c3f</id>
<content type='text'>
The completion of a pq operation is notified with a null descriptor
appended to the end of the chain.  This descriptor needs to be visible
to dma clients otherwise the client is precluded from ensuring all
operations are quiesced before freeing channel resources, i.e. due to
descriptor polling it may get the completion notification ahead of the
interrupt delivered by the null descriptor.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>async_tx: build-time toggling of async_{syndrome,xor}_val dma support</title>
<updated>2009-11-20T06:21:03Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2009-11-20T00:10:37Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=7b3cc2b1fc2066391e498f3387204908c4eced21'/>
<id>urn:sha1:7b3cc2b1fc2066391e498f3387204908c4eced21</id>
<content type='text'>
ioat3.2 does not support asynchronous error notifications which makes
the driver experience latencies when non-zero pq validate results are
expected.  Provide a mechanism for turning off async_xor_val and
async_syndrome_val via Kconfig.  This approach is generally useful for
any driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like
to force the async_tx api to fall back to the synchronous path for
certain operations.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;

</content>
</entry>
</feed>
