<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/dma/dmaengine.c, branch v3.0.62</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/drivers/dma/dmaengine.c?h=v3.0.62</id>
<link rel='self' href='https://git.amat.us/linux/atom/drivers/dma/dmaengine.c?h=v3.0.62'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2010-10-08T00:08:32Z</updated>
<entry>
<title>async_tx: make async_tx channel switching opt-in</title>
<updated>2010-10-08T00:08:32Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2010-10-07T23:44:50Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=5fc6d897fde352bad5db5767e7260741a8cdd9e9'/>
<id>urn:sha1:5fc6d897fde352bad5db5767e7260741a8cdd9e9</id>
<content type='text'>
The majority of drivers in drivers/dma/ will never establish cross
channel operation chains and do not need the extra overhead in struct
dma_async_tx_descriptor.  Make channel switching opt-in by default.

Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Cc: Ira Snyder &lt;iws@ovro.caltech.edu&gt;
Cc: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Cc: Saeed Bishara &lt;saeed@marvell.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branches 'dma40', 'pl08x', 'fsldma', 'imx' and 'intel-mid' into dmaengine</title>
<updated>2010-10-07T22:19:01Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2010-10-07T22:19:01Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=6391987d6f8ced7d0fafaa1440dcc57bb4b34d8f'/>
<id>urn:sha1:6391987d6f8ced7d0fafaa1440dcc57bb4b34d8f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dma: add support for scatterlist to scatterlist copy</title>
<updated>2010-10-07T21:41:40Z</updated>
<author>
<name>Ira Snyder</name>
<email>iws@ovro.caltech.edu</email>
</author>
<published>2010-09-30T11:46:44Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=a86ee03ce6f279ebe581a7a8c0c4393eaeb789ee'/>
<id>urn:sha1:a86ee03ce6f279ebe581a7a8c0c4393eaeb789ee</id>
<content type='text'>
This adds support for scatterlist to scatterlist DMA transfers. A
similar interface is exposed by the fsldma driver (through the DMA_SLAVE
API) and by the ste_dma40 driver (through an exported function).

This patch paves the way for making this type of copy operation a part
of the generic DMAEngine API. Futher patches will add support in
individual drivers.

Signed-off-by: Ira W. Snyder &lt;iws@ovro.caltech.edu&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: add possibility for cyclic transfers</title>
<updated>2010-10-05T22:49:26Z</updated>
<author>
<name>Sascha Hauer</name>
<email>s.hauer@pengutronix.de</email>
</author>
<published>2010-09-30T13:56:32Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=782bc950d84e404422ba21008fd51ee894c8d231'/>
<id>urn:sha1:782bc950d84e404422ba21008fd51ee894c8d231</id>
<content type='text'>
Cyclic transfers are useful for audio where a single buffer divided
in periods has to be transfered endlessly until stopped. After being
prepared the transfer is started using the dma_async_descriptor-&gt;tx_submit
function. dma_async_descriptor-&gt;callback is called after each period.
The transfer is stopped using the DMA_TERMINATE_ALL callback.
While being used for cyclic transfers the channel cannot be used
for other transfer types.

Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
Cc: Haavard Skinnemoen &lt;haavard.skinnemoen@atmel.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'ioat' into dmaengine</title>
<updated>2010-05-17T23:30:58Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2010-05-17T23:30:58Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=0b28330e39bbe0ffee4c56b09fc415fcec595ea3'/>
<id>urn:sha1:0b28330e39bbe0ffee4c56b09fc415fcec595ea3</id>
<content type='text'>
</content>
</entry>
<entry>
<title>async_tx: trim dma_async_tx_descriptor in 'no channel switch' case</title>
<updated>2010-05-17T23:24:16Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2010-05-17T23:24:16Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=caa20d974c86af496b419eef70010e63b7fab7ac'/>
<id>urn:sha1:caa20d974c86af496b419eef70010e63b7fab7ac</id>
<content type='text'>
Saves 24 bytes per descriptor (64-bit) when the channel-switching
capabilities of async_tx are not required.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>DMA ENGINE: Do not reset 'private' of channel</title>
<updated>2010-05-17T08:33:56Z</updated>
<author>
<name>Jassi Brar</name>
<email>jassi.brar@samsung.com</email>
</author>
<published>2010-05-04T09:22:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=cc05ea0cd63437da2033b3ce6e033b1f1aaaf640'/>
<id>urn:sha1:cc05ea0cd63437da2033b3ce6e033b1f1aaaf640</id>
<content type='text'>
The member 'private' of 'struct dma_chan' is meant for passing
data between client and the controller driver.

The DMA client driver may point it to platform specific stuff after
acquiring the channel. So, it is the responsiblity of the same code
to reset it, if it must.

The DMA engine doesn't set it and hence, shouldn't reset it either.

This reseting of private by DMA Engine comes in the way of implementing
default channel settings during DMAC probe. That capability is useful
for not having the clients to always provide platform specific data,
like Rx/Tx FIFO addresses, which usually doesn't change across channel
requests.

Signed-off-by: Jassi Brar &lt;jassi.brar@samsung.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h</title>
<updated>2010-03-30T13:02:32Z</updated>
<author>
<name>Tejun Heo</name>
<email>tj@kernel.org</email>
</author>
<published>2010-03-24T08:04:11Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=5a0e3ad6af8660be21ca98a971cd00f331318c05'/>
<id>urn:sha1:5a0e3ad6af8660be21ca98a971cd00f331318c05</id>
<content type='text'>
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -&gt; slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.

Signed-off-by: Tejun Heo &lt;tj@kernel.org&gt;
Guess-its-ok-by: Christoph Lameter &lt;cl@linux-foundation.org&gt;
Cc: Ingo Molnar &lt;mingo@redhat.com&gt;
Cc: Lee Schermerhorn &lt;Lee.Schermerhorn@hp.com&gt;
</content>
</entry>
<entry>
<title>DMAENGINE: generic channel status v2</title>
<updated>2010-03-26T23:50:49Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@stericsson.com</email>
</author>
<published>2010-03-26T23:50:49Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=0793448187643b50af89d36b08470baf45a3cab4'/>
<id>urn:sha1:0793448187643b50af89d36b08470baf45a3cab4</id>
<content type='text'>
Convert the device_is_tx_complete() operation on the
DMA engine to a generic device_tx_status()operation which
can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,
DMA_TX_PAUSED.

[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Acked-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
Cc: Maciej Sosnowski &lt;maciej.sosnowski@intel.com&gt;
Cc: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Li Yang &lt;leoli@freescale.com&gt;
Cc: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Cc: Paul Mundt &lt;lethal@linux-sh.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Haavard Skinnemoen &lt;haavard.skinnemoen@atmel.com&gt;
Cc: Magnus Damm &lt;damm@opensource.se&gt;
Cc: Liam Girdwood &lt;lrg@slimlogic.co.uk&gt;
Cc: Joe Perches &lt;joe@perches.com&gt;
Cc: Roland Dreier &lt;rdreier@cisco.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>DMAENGINE: generic slave control v2</title>
<updated>2010-03-26T23:44:01Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@stericsson.com</email>
</author>
<published>2010-03-26T23:44:01Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=c3635c78e500a52c9fcd55de381a72928d9e054d'/>
<id>urn:sha1:c3635c78e500a52c9fcd55de381a72928d9e054d</id>
<content type='text'>
Convert the device_terminate_all() operation on the
DMA engine to a generic device_control() operation
which can now optionally support also pausing and
resuming DMA on a certain channel. Implemented for the
COH 901 318 DMAC as an example.

[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Acked-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
Cc: Maciej Sosnowski &lt;maciej.sosnowski@intel.com&gt;
Cc: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Li Yang &lt;leoli@freescale.com&gt;
Cc: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Cc: Paul Mundt &lt;lethal@linux-sh.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Haavard Skinnemoen &lt;haavard.skinnemoen@atmel.com&gt;
Cc: Magnus Damm &lt;damm@opensource.se&gt;
Cc: Liam Girdwood &lt;lrg@slimlogic.co.uk&gt;
Cc: Joe Perches &lt;joe@perches.com&gt;
Cc: Roland Dreier &lt;rdreier@cisco.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
</feed>
