linux/drivers/clk, branch v3.12.10

clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

2014-01-15T23:31:42Z

commit 97c3557c3e0413efb1f021f582d1459760e22727 upstream. The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by: Andrew Bresticker Signed-off-by: Sachin Kamat Acked-by: Mike Turquette Signed-off-by: Tomasz Figa Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

2014-01-15T23:31:42Z

commit 2feed5aecf5f367b92bd6b6e92afe9e3de466907 upstream. The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by: Abhilash Kesavan Acked-by: Mike Turquette [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5250: Add MDMA0 clocks

2014-01-15T23:31:42Z

commit 8fb9aeb7a71ef4f3e0613d459a2e1366a7a90469 upstream. Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by: Abhilash Kesavan Acked-by: Mike Turquette [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5250: Fix ACP gate register offset

2014-01-15T23:31:41Z

commit 3bf34666a0cce5234ac677ed2fbe5cea82c71329 upstream. The CLK_GATE_IP_ACP register offset is incorrectly listed making definition of g2d clock incorrect, which may lead to system failures when trying to use G2D on systems on which firmware gates this clock by default. Fix this and the register ordering as well. Signed-off-by: Abhilash Kesavan Acked-by: Mike Turquette [t.figa: Updated patch description.] Signed-off-by: Tomasz Figa Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos4: Correct SRC_MFC register

2014-01-15T23:31:41Z

commit 5fdd1b56be51b1ec4dbde5b213d649ac717442da upstream. The SRC_MFC register offset was incorrect, which could cause have caused wrong calculation of rate of sclk_mfc clock, that could in turn lead to incorrect operation of MFC. This patch corrects it. Signed-off-by: Seung-Woo Kim Acked-by: Mike Turquette [t.figa: Updated patch description] Signed-off-by: Tomasz Figa Signed-off-by: Greg Kroah-Hartman

clk: clk-divider: fix divisor > 255 bug

2014-01-15T23:31:41Z

commit 778037e1ccb75609846deca9e419449c1dc137fa upstream. Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers) merged in v3.6 added the _get_val function to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high. E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz. Signed-off-by: James Hogan Cc: Rajendra Nayak Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette Signed-off-by: Greg Kroah-Hartman

clk: fixup argument order when setting VCO parameters

2013-10-08T06:01:07Z

The order of arguments in the call to vco_set() for the ICST clocks appears to have been switched in error, which results in the VCO not being initialised correctly. This in turn stops the integrated LCD on things like Integrator/CP from working correctly. This patch fixes the order and restores the expected functionality. Reviewed-by: Linus Walleij Signed-off-by: Jonathan Austin Signed-off-by: Mike Turquette Cc: stable@vger.kernel.org

clk: socfpga: Fix incorrect sdmmc clock name

2013-10-08T01:37:49Z

The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this, the SD driver was getting the incorrect clock value. This prevented the SD driver from initializing correctly. Signed-off-by: Dinh Nguyen CC: Arnd Bergmann CC: Olof Johansson Reviewed-by: Pavel Machek Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette

clk: armada-370: fix tclk frequencies

2013-10-07T00:39:46Z

This patch fixes the tclk frequency array for the Armada-370 SoC. This bug has been introduced by commit 6b72333d ("clk: mvebu: add Armada 370 SoC-centric clock init"). A wrong tclk frequency affects the following drivers: mvsdio, mvneta, i2c-mv64xxx and mvebu-devbus. This list may be incomplete. About the mvneta Ethernet driver, note that the tclk frequency is used to compute the Rx time coalescence. Then, this bug harms the coalescence configuration and also degrades the networking performances with the default values. Signed-off-by: Simon Guinot Cc: Andrew Lunn Cc: Gregory CLEMENT Cc: Sebastian Hesselbarth Acked-by: Jason Cooper Cc: stable@vger.kernel.org Signed-off-by: Michael Turquette

clk: nomadik: set all timers to use 2.4 MHz TIMCLK

2013-10-02T04:39:56Z

This fixes a regression for the Nomadik on the main system timers. The Nomadik seemed a bit slow and its heartbeat wasn't looking healthy. And it was not strange, because it has been connected to the 32768 Hz clock at boot, while being told by the clock driver that it was 2.4MHz. Actually connect the TIMCLK to 2.4MHz by default as this is what we want for nice scheduling, clocksource and clock event. Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij Signed-off-by: Mike Turquette