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<title>linux/drivers/base/regmap, branch v3.7-rc2</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/drivers/base/regmap?h=v3.7-rc2</id>
<link rel='self' href='https://git.amat.us/linux/atom/drivers/base/regmap?h=v3.7-rc2'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2012-09-22T16:02:05Z</updated>
<entry>
<title>Merge remote-tracking branches 'regmap/topic/cache' and 'regmap/topic/irq' into regmap-next</title>
<updated>2012-09-22T16:02:05Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2012-09-22T16:02:05Z</published>
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<id>urn:sha1:613dac31a612f9417bd1b1438acebbc3b8f9073e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>regmap: no need primary handler for nested irq</title>
<updated>2012-09-09T03:05:45Z</updated>
<author>
<name>Yunfan Zhang</name>
<email>yfzhang@marvell.com</email>
</author>
<published>2012-09-08T10:53:25Z</published>
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<id>urn:sha1:81380739516730124067576c9cc9f2418be5bf36</id>
<content type='text'>
The primary handler will NOT be called if the interrupt nests into
another interrupt thread. Remove it to avoid confusing.

Signed-off-by: Yunfan Zhang &lt;yfzhang@marvell.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: irq: Add mask invert flag for enable register</title>
<updated>2012-08-30T18:13:41Z</updated>
<author>
<name>Xiaofan Tian</name>
<email>tianxf@marvell.com</email>
</author>
<published>2012-08-30T09:03:35Z</published>
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<id>urn:sha1:36ac914ba2a5f1a14c5e0bf5d33bc20016d50940</id>
<content type='text'>
Currently, regmap will write 1 to mask_base to mask
an interrupt and write 0 to unmask it.

But some chips do not have an interrupt mask register,
and only have interrupt enable register.
Then we should write 0 to disable interrupt and 1 to enable.

So add an mask_invert flag to handle this.
If it is not set, behavior is same as previous.
If set it to 1, the mask value will be inverted
before written to mask_base

Signed-off-by: Xiaofan Tian &lt;tianxf@marvell.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: irq: Enable devices for runtime PM while handling interrupts</title>
<updated>2012-08-07T19:29:45Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2012-07-24T14:41:19Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=0c00c50b41a9a6ee83eb16fb5c6c22e5115391b8'/>
<id>urn:sha1:0c00c50b41a9a6ee83eb16fb5c6c22e5115391b8</id>
<content type='text'>
Some devices need to have a runtime PM reference while handling interrupts
to ensure that the register I/O is available. Support this with a flag in
the chip.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: irq: initialize all irqs to wake disabled</title>
<updated>2012-08-04T11:13:54Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-08-01T19:57:24Z</published>
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<id>urn:sha1:40052ca0c243d101cfadd65936f60ef81df10b02</id>
<content type='text'>
The kerneldoc for irq_set_irq_wake() says:

    Enable/disable power management wakeup mode, which is
    disabled by default.

regmap_irq_set_wake() clears bits to enable wake for an interrupt,
and sets bits to disable wake. Hence, we should set all bits in
wake_buf initially, to mirror the expected disabled state.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: set MASK_ON_SUSPEND/SKIP_SET_WAKE if no wake_base</title>
<updated>2012-08-04T11:13:53Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-08-01T17:40:49Z</published>
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<id>urn:sha1:685879f4b2036e58c1a0cdaaee2b155d3c965461</id>
<content type='text'>
If a regmap-irq chip has no wake base:

* There's no point calling .irq_set_wake, hence IRQCHIP_SKIP_SET_WAKE.

* If some IRQs in the chip are enabled for wake and some aren't, we
  should mask those interrupts that are not wake enabled, so that if
  they occur during suspend, the system is not awoken. Hence,
  IRQCHIP_MASK_ON_SUSPEND.

Note that IRQCHIP_MASK_ON_SUSPEND is handled by check_wakeup_irqs(),
which always iterates over every single interrupt in the system,
irrespective of whether an interrupt is a child of a controller whose
output interrupt has no wake-enabled inputs and hence is presumably
masked itself. Hence this change might cause interrupt unnecessary
masking operations and associated register I/O.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: name irq_chip based on regmap_irq_chip's name</title>
<updated>2012-08-04T11:13:53Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-08-01T17:40:48Z</published>
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<id>urn:sha1:ca142750f8ac3d01e45909e624ca783779894640</id>
<content type='text'>
This is intended to give each irq_chip a useful name, rather than hard-
coding them all as "regmap".

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: store irq_chip inside regmap_irq_chip_data</title>
<updated>2012-08-04T11:13:53Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-08-01T17:40:47Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=7ac140ec426ed304237205be77f99eedfc1186b5'/>
<id>urn:sha1:7ac140ec426ed304237205be77f99eedfc1186b5</id>
<content type='text'>
This will allow later patches to adjust portions of the irq_chip
individually for each regmap_irq_chip that is created.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: irq: Only update mask bits when doing initial mask</title>
<updated>2012-08-04T11:13:53Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2012-08-01T19:29:14Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=0eb46ad0c8d60943c1f46cef795fc537fbffd177'/>
<id>urn:sha1:0eb46ad0c8d60943c1f46cef795fc537fbffd177</id>
<content type='text'>
Don't write the full register, it's possible there's bits other than the
masks in the same register which we shouldn't be changing.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
Tested-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
</content>
</entry>
<entry>
<title>regmap: fix some error messages to take account of irq_reg_stride</title>
<updated>2012-08-04T11:13:53Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-07-27T19:01:54Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=16032624f511b2fac0671cba5e7da40aa7e73a66'/>
<id>urn:sha1:16032624f511b2fac0671cba5e7da40aa7e73a66</id>
<content type='text'>
A number of places in the code were printing error messages that included
the address of a register, but were not calculating the register address
in the same way as the access to the register. Use a temporary to solve
this.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
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