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<title>linux/arch, branch v3.0.19</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch?h=v3.0.19</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch?h=v3.0.19'/>
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<updated>2012-02-03T17:19:04Z</updated>
<entry>
<title>net: bpf_jit: fix divide by 0 generation</title>
<updated>2012-02-03T17:19:04Z</updated>
<author>
<name>Eric Dumazet</name>
<email>eric.dumazet@gmail.com</email>
</author>
<published>2012-01-18T07:21:42Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=d020b1d3d3379d183d0649cdc2f6de9131268419'/>
<id>urn:sha1:d020b1d3d3379d183d0649cdc2f6de9131268419</id>
<content type='text'>
[ Upstream commit d00a9dd21bdf7908b70866794c8313ee8a5abd5c ]

Several problems fixed in this patch :

1) Target of the conditional jump in case a divide by 0 is performed
   by a bpf is wrong.

2) Must 'generate' the full function prologue/epilogue at pass=0,
   or else we can stop too early in pass=1 if the proglen doesnt change.
   (if the increase of prologue/epilogue equals decrease of all
    instructions length because some jumps are converted to near jumps)

3) Change the wrong length detection at the end of code generation to
   issue a more explicit message, no need for a full stack trace.

Reported-by: Phil Oester &lt;kernel@linuxace.com&gt;
Signed-off-by: Eric Dumazet &lt;eric.dumazet@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards</title>
<updated>2012-02-03T17:18:58Z</updated>
<author>
<name>Will Deacon</name>
<email>will.deacon@arm.com</email>
</author>
<published>2012-01-20T11:10:18Z</published>
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<id>urn:sha1:95086de856ca703588967f63cc54b8059db55888</id>
<content type='text'>
commit 612539e81f655f6ac73c7af1da8701c1ee618aee upstream.

On v7, we use the same cache maintenance instructions for data lines
as for unified lines. This was not the case for v6, where HARVARD_CACHE
was defined to indicate the L1 cache topology.

This patch removes the erroneous compile-time check for HARVARD_CACHE in
proc-v7.S, ensuring that we perform I-side invalidation at boot.

Reported-and-Acked-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;

Acked-by: Catalin Marinas &lt;Catalin.Marinas@arm.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>mach-ux500: enable ARM errata 764369</title>
<updated>2012-02-03T17:18:57Z</updated>
<author>
<name>Srinidhi KASAGAR</name>
<email>srinidhi.kasagar@stericsson.com</email>
</author>
<published>2012-01-12T05:37:43Z</published>
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<id>urn:sha1:4e29fa93520b401b81a719fe053f06c6937d5b66</id>
<content type='text'>
commit d65015f7c5c5be9fd3f5e567889c844ba81bdc9c upstream.

This applies ARM errata 764369 for all ux500 platforms.

Signed-off-by: Srinidhi Kasagar &lt;srinidhi.kasagar@stericsson.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>x86/microcode_amd: Add support for CPU family specific container files</title>
<updated>2012-02-03T17:18:56Z</updated>
<author>
<name>Andreas Herrmann</name>
<email>andreas.herrmann3@amd.com</email>
</author>
<published>2012-01-20T16:44:12Z</published>
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<id>urn:sha1:231f0496129d5d41ae77cc2410e3cea97540cd7b</id>
<content type='text'>
commit 5b68edc91cdc972c46f76f85eded7ffddc3ff5c2 upstream.

We've decided to provide CPU family specific container files
(starting with CPU family 15h). E.g. for family 15h we have to
load microcode_amd_fam15h.bin instead of microcode_amd.bin

Rationale is that starting with family 15h patch size is larger
than 2KB which was hard coded as maximum patch size in various
microcode loaders (not just Linux).

Container files which include patches larger than 2KB cause
different kinds of trouble with such old patch loaders. Thus we
have to ensure that the default container file provides only
patches with size less than 2KB.

Signed-off-by: Andreas Herrmann &lt;andreas.herrmann3@amd.com&gt;
Cc: Borislav Petkov &lt;borislav.petkov@amd.com&gt;
Cc: &lt;stable@kernel.org&gt;
Link: http://lkml.kernel.org/r/20120120164412.GD24508@alberich.amd.com
[ documented the naming convention and tidied the code a bit. ]
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>x86/uv: Fix uv_gpa_to_soc_phys_ram() shift</title>
<updated>2012-02-03T17:18:55Z</updated>
<author>
<name>Russ Anderson</name>
<email>rja@sgi.com</email>
</author>
<published>2012-01-19T02:07:54Z</published>
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<id>urn:sha1:8c6f009ebfcdae4196be7e456c99ad44eb013420</id>
<content type='text'>
commit 5a51467b146ab7948d2f6812892eac120a30529c upstream.

uv_gpa_to_soc_phys_ram() was inadvertently ignoring the
shift values.  This fix takes the shift into account.

Signed-off-by: Russ Anderson &lt;rja@sgi.com&gt;
Link: http://lkml.kernel.org/r/20120119020753.GA7228@sgi.com
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>score: fix off-by-one index into syscall table</title>
<updated>2012-01-26T01:25:04Z</updated>
<author>
<name>Dan Rosenberg</name>
<email>drosenberg@vsecurity.com</email>
</author>
<published>2012-01-20T22:34:27Z</published>
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<id>urn:sha1:72a82010500dea88b2d786a76b063a871e2a4603</id>
<content type='text'>
commit c25a785d6647984505fa165b5cd84cfc9a95970b upstream.

If the provided system call number is equal to __NR_syscalls, the
current check will pass and a function pointer just after the system
call table may be called, since sys_call_table is an array with total
size __NR_syscalls.

Whether or not this is a security bug depends on what the compiler puts
immediately after the system call table.  It's likely that this won't do
anything bad because there is an additional NULL check on the syscall
entry, but if there happens to be a non-NULL value immediately after the
system call table, this may result in local privilege escalation.

Signed-off-by: Dan Rosenberg &lt;drosenberg@vsecurity.com&gt;
Cc: Chen Liqin &lt;liqin.chen@sunplusct.com&gt;
Cc: Lennox Wu &lt;lennox.wu@gmail.com&gt;
Cc: Eugene Teo &lt;eugeneteo@kernel.sg&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86/UV2: Fix BAU destination timeout initialization</title>
<updated>2012-01-26T01:25:01Z</updated>
<author>
<name>Cliff Wickman</name>
<email>cpw@sgi.com</email>
</author>
<published>2012-01-16T21:18:48Z</published>
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<id>urn:sha1:415b95df641c998a7cf15c916047f338ab2ce87b</id>
<content type='text'>
commit d059f9fa84a30e04279c6ff615e9e2cf3b260191 upstream.

Move the call to enable_timeouts() forward so that
BAU_MISC_CONTROL is initialized before using it in
calculate_destination_timeout().

Fix the calculation of a BAU destination timeout
for UV2 (in calculate_destination_timeout()).

Signed-off-by: Cliff Wickman &lt;cpw@sgi.com&gt;
Link: http://lkml.kernel.org/r/20120116211848.GB5767@sgi.com
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>ACPI, ia64: Use SRAT table rev to use 8bit or 16/32bit PXM fields (ia64)</title>
<updated>2012-01-26T01:24:58Z</updated>
<author>
<name>Kurt Garloff</name>
<email>kurt@garloff.de</email>
</author>
<published>2012-01-17T09:21:49Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=0076d42a31bac7853d3c77c3858d2685f6fe8f2d'/>
<id>urn:sha1:0076d42a31bac7853d3c77c3858d2685f6fe8f2d</id>
<content type='text'>
commit 9f10f6a520deb3639fac78d81151a3ade88b4e7f upstream.

In SRAT v1, we had 8bit proximity domain (PXM) fields; SRAT v2 provides
32bits for these. The new fields were reserved before.
According to the ACPI spec, the OS must disregrard reserved fields.

ia64 did handle the PXM fields almost consistently, but depending on
sgi's sn2 platform. This patch leaves the sn2 logic in, but does also
use 16/32 bits for PXM if the SRAT has rev 2 or higher.

The patch also adds __init to the two pxm accessor functions, as they
access __initdata now and are called from an __init function only anyway.

Note that the code only uses 16 bits for the PXM field in the processor
proximity field; the patch does not address this as 16 bits are more than
enough.

Signed-off-by: Kurt Garloff &lt;kurt@garloff.de&gt;
Signed-off-by: Len Brown &lt;len.brown@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>ACPI, x86: Use SRAT table rev to use 8bit or 32bit PXM fields (x86/x86-64)</title>
<updated>2012-01-26T01:24:57Z</updated>
<author>
<name>Kurt Garloff</name>
<email>kurt@garloff.de</email>
</author>
<published>2012-01-17T09:20:31Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=ef9a04d5b336853aeb3f3975c4e52b07c1c4d3ec'/>
<id>urn:sha1:ef9a04d5b336853aeb3f3975c4e52b07c1c4d3ec</id>
<content type='text'>
commit cd298f60a2451a16e0f077404bf69b62ec868733 upstream.

In SRAT v1, we had 8bit proximity domain (PXM) fields; SRAT v2 provides
32bits for these. The new fields were reserved before.
According to the ACPI spec, the OS must disregrard reserved fields.

x86/x86-64 was rather inconsistent prior to this patch; it used 8 bits
for the pxm field in cpu_affinity, but 32 bits in mem_affinity.
This patch makes it consistent: Either use 8 bits consistently (SRAT
rev 1 or lower) or 32 bits (SRAT rev 2 or higher).

cc: x86@kernel.org
Signed-off-by: Kurt Garloff &lt;kurt@garloff.de&gt;
Signed-off-by: Len Brown &lt;len.brown@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86, UV: Update Boot messages for SGI UV2 platform</title>
<updated>2012-01-26T01:24:49Z</updated>
<author>
<name>Jack Steiner</name>
<email>steiner@sgi.com</email>
</author>
<published>2012-01-06T19:19:00Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=15274414badc6ef0a893454e7102f3753f2c1ccd'/>
<id>urn:sha1:15274414badc6ef0a893454e7102f3753f2c1ccd</id>
<content type='text'>
commit da517a08ac5913cd80ce3507cddd00f2a091b13c upstream.

SGI UV systems print a message during boot:

	UV: Found &lt;num&gt; blades

Due to packaging changes, the blade count is not accurate for
on the next generation of the platform. This patch corrects the
count.

Signed-off-by: Jack Steiner &lt;steiner@sgi.com&gt;
Link: http://lkml.kernel.org/r/20120106191900.GA19772@sgi.com
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
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