linux/arch, branch v2.6.23.16

ia64: Fix unaligned handler for floating point instructions with base update

2008-02-08T20:01:46Z

commit 1a499150e4ec1299232e24389f648d059ce5617a in mainline. [IA64] Fix unaligned handler for floating point instructions with base update The compiler team did the hard work for this distilling a problem in large fortran application which showed up when applied to a 290MB input data set down to this instruction: ldfd f34=[r17],-8 Which they noticed incremented r17 by 0x10 rather than decrementing it by 8 when the value in r17 caused an unaligned data fault. I tracked it down to some bad instruction decoding in unaligned.c. The code assumes that the 'x' bit can determine whether the instruction is an "ldf" or "ldfp" ... which it is for opcode=6 (see table 4-29 on page 3:302 of the SDM). But for opcode=7 the 'x' bit is irrelevent, all variants are "ldf" instructions (see table 4-36 on page 3:306). Note also that interpreting the instruction as "ldfp" means that the "paired" floating point register (f35 in the example here) will also be corrupted. Signed-off-by: Tony Luck Signed-off-by: Greg Kroah-Hartman

PM: ACPI and APM must not be enabled at the same time

2008-02-08T20:01:32Z

patch 9f9adecd2d0e4f88fa0e8cb06c6ec207748df70a in mainline. ACPI and APM used "pm_active" to guarantee that they would not be simultaneously active. But pm_active was recently moved under CONFIG_PM_LEGACY, so that without CONFIG_PM_LEGACY, pm_active became a NOP -- allowing ACPI and APM to both be simultaneously enabled. This caused unpredictable results, including boot hangs. Further, the code under CONFIG_PM_LEGACY is scheduled for removal. So replace pm_active with pm_flags. pm_flags depends only on CONFIG_PM, which is present for both CONFIG_APM and CONFIG_ACPI. http://bugzilla.kernel.org/show_bug.cgi?id=9194 Signed-off-by: Len Brown Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman

SPARC64: Implement pci_resource_to_user()

2008-02-08T20:01:28Z

[SPARC64]: Implement pci_resource_to_user() [ Upstream commit: bcea1db16ba1c45ccebb3bfb8441642d1342c4d5 ] This makes libpciaccess able to mmap() resources of the device properly. Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman

SPARC64: Fix two kernel linear mapping setup bugs.

2008-02-08T20:01:13Z

[SPARC64]: Fix two kernel linear mapping setup bugs. [ Upstream commit: 8f361453d8e9a67c85b2cf9b93c642c2d8fe0462 ] This was caught and identified by Greg Onufer. Since we setup the 256M/4M bitmap table after taking over the trap table, it's possible for some 4M mapping to get loaded in the TLB beforhand which later will be 256M mappings. This can cause illegal TLB multiple-match conditions. Fix this by setting up the bitmap before we take over the trap table. Next, __flush_tlb_all() was not doing anything on hypervisor platforms. Fix by adding sun4v_mmu_demap_all() and calling it. Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman

SPARC64: Fix memory controller register access when non-SMP.

2008-02-08T20:01:11Z

[SPARC64]: Fix memory controller register access when non-SMP. [ Upstream commit: b332b8bc9c67165eabdfc7d10b4a2e4cc9f937d0 ] get_cpu() always returns zero on non-SMP builds, but we really want the physical cpu number in this code in order to do the right thing. Based upon a non-SMP kernel boot failure report from Bernd Zeimetz. Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman

SPARC64: Fix sparc64 cpu cross call hangs.

2008-02-08T20:01:05Z

[SPARC64]: Fix endless loop in cheetah_xcall_deliver(). [ Upsteam commit: 0de56d1ab83323d604d95ca193dcbd28388dbabb ] We need to mask out the proper bits when testing the dispatch status register else we can see unrelated NACK bits from previous cross call sends. Signed-off-by: David S. Miller

x86 setup: add a near jump to serialize %cr0 on 386/486

2007-12-14T17:50:58Z

patch 7ed192906a2144ebc8ca2925a85d27b9c5355668 in mainline. The 386 and 486 needs a jump immediately after setting %cr0 in order to serialize the pipeline. Signed-off-by: H. Peter Anvin Signed-off-by: Greg Kroah-Hartman

x86: fix freeze in x86_64 RTC update code in time_64.c

2007-11-26T17:42:32Z

patch c399da0d97e06803e51085ec076b63a3168aad1b in mainline. x86: fix freeze in x86_64 RTC update code in time_64.c Fix hard freeze on x86_64 when the ntpd service calls update_persistent_clock() A repeatable but randomly timed freeze has been happening in Fedora 6 and 7 for the last year, whenever I run the ntpd service on my AMD64x2 HP Pavilion dv9000z laptop. This freeze is due to the use of spin_lock(&rtc_lock) under the assumption (per a bad comment) that set_rtc_mmss is called only with interrupts disabled. The call from ntp.c to update_persistent_clock is made with interrupts enabled. [ tglx@linutronix.de: ported to 2.6.23.stable ] Signed-off-by: David P. Reed Signed-off-by: Thomas Gleixner Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman

x86: return correct error code from child_rip in x86_64 entry.S

2007-11-26T17:42:31Z

patch 1c5b5cfd290b6cb7c67020ef420e275f746a7236 in mainline. x86: return correct error code from child_rip in x86_64 entry.S Right now register edi is just cleared before calling do_exit. That is wrong because correct return value will be ignored. Value from rax should be copied to rdi instead of clearing edi. AK: changed to 32bit move because it's strictly an int [ tglx: arch/x86 adaptation ] Signed-off-by: Andrey Mirkin Signed-off-by: Andi Kleen Signed-off-by: Ingo Molnar Signed-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman

x86: NX bit handling in change_page_attr()

2007-11-26T17:42:31Z

patch 84e0fdb1754d066dd0a8b257de7299f392d1e727 in mainline. x86: NX bit handling in change_page_attr() This patch fixes a bug of change_page_attr/change_page_attr_addr on Intel x86_64 CPUs. After changing page attribute to be executable with these functions, the page remains un-executable on Intel x86_64 CPU. Because on Intel x86_64 CPU, only if the "NX" bits of all four level page tables are cleared, the corresponding page is executable (refer to section 4.13.2 of Intel 64 and IA-32 Architectures Software Developer's Manual). So, the bug is fixed through clearing the "NX" bit of PMD when splitting the huge PMD. Signed-off-by: Huang Ying Cc: Andi Kleen Signed-off-by: Andrew Morton Signed-off-by: Ingo Molnar Signed-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman