<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch, branch mybooklive</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch?h=mybooklive</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch?h=mybooklive'/>
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<updated>2014-08-13T23:39:02Z</updated>
<entry>
<title>gpl-source-mybooklive-02.11.09-053.zip</title>
<updated>2014-08-13T23:39:02Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T23:39:02Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=18351c6816244feb6bcb75d2eb22681fd6941b31'/>
<id>urn:sha1:18351c6816244feb6bcb75d2eb22681fd6941b31</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gpl-source-mybooklive-02.10.09-124.zip</title>
<updated>2014-08-13T23:32:56Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T23:32:56Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=cddfc3baae08e24185c7716434452ebbd404cd39'/>
<id>urn:sha1:cddfc3baae08e24185c7716434452ebbd404cd39</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gpl-source-mybooklive-020202.zip</title>
<updated>2014-08-13T23:11:53Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T23:11:53Z</published>
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<content type='text'>
</content>
</entry>
<entry>
<title>gpl-source-mybooklive-020035.zip</title>
<updated>2014-08-13T23:04:11Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T23:04:11Z</published>
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<id>urn:sha1:f05c100b6a7051106229cda5a845e94e36e71b17</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gpl-source-mybooklive-010203-update.zip</title>
<updated>2014-08-13T21:29:15Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T21:29:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=205ac4d83fc388c1e2d0bb590a2a36e9a4c2fd78'/>
<id>urn:sha1:205ac4d83fc388c1e2d0bb590a2a36e9a4c2fd78</id>
<content type='text'>
</content>
</entry>
<entry>
<title>gpl-source-mybooklive-010002-update.zip</title>
<updated>2014-08-13T21:14:13Z</updated>
<author>
<name>David Barksdale</name>
<email>amatus@amatus.name</email>
</author>
<published>2014-08-13T21:14:13Z</published>
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<id>urn:sha1:ace6c6d243016e272050787c14e27a83ecd94a25</id>
<content type='text'>
</content>
</entry>
<entry>
<title>x86: Fix sched_clock_cpu for systems with unsynchronized TSC</title>
<updated>2010-04-01T22:58:57Z</updated>
<author>
<name>Dimitri Sivanich</name>
<email>sivanich@sgi.com</email>
</author>
<published>2010-03-01T17:48:15Z</published>
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<id>urn:sha1:847d52cc4a3e149949df66d7484aba999dc61e19</id>
<content type='text'>
commit 14be1f7454ea96ee614467a49cf018a1a383b189 upstream.

On UV systems, the TSC is not synchronized across blades.  The
sched_clock_cpu() function is returning values that can go
backwards  (I've seen as much as 8 seconds) when switching
between cpus.

As each cpu comes up, early_init_intel() will currently set the
sched_clock_stable flag true.  When mark_tsc_unstable() runs, it
clears the flag, but this only occurs once (the first time a cpu
comes up whose TSC is not synchronized with cpu 0).  After this,
early_init_intel() will set the flag again as the next cpu comes
up.

Only set sched_clock_stable if tsc has not been marked unstable.

Signed-off-by: Dimitri Sivanich &lt;sivanich@sgi.com&gt;
Acked-by: Venkatesh Pallipadi &lt;venkatesh.pallipadi@intel.com&gt;
Acked-by: Peter Zijlstra &lt;a.p.zijlstra@chello.nl&gt;
LKML-Reference: &lt;20100301174815.GC8224@sgi.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>sh: Fix zImage boot using fixed PMB.</title>
<updated>2010-04-01T22:58:55Z</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>iwamatsu@nigauri.org</email>
</author>
<published>2010-03-20T07:42:54Z</published>
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<id>urn:sha1:f15a9d8a07f97af708304414910e7daeb5e5936d</id>
<content type='text'>
commit 319c2cc761505ee54a9536c5d0b9c2ee3fb33866 upstream.

Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu.nobuhiro@renesas.com&gt;
Signed-off-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86, amd: Restrict usage of c1e_idle()</title>
<updated>2010-04-01T22:58:48Z</updated>
<author>
<name>Andreas Herrmann</name>
<email>andreas.herrmann3@amd.com</email>
</author>
<published>2010-03-19T11:09:22Z</published>
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<id>urn:sha1:341badb52110ba8fff671b3078da7ff45440fc4c</id>
<content type='text'>
commit 035a02c1e1de31888e8b6adac0ff667971ac04db upstream.

Currently c1e_idle returns true for all CPUs greater than or equal to
family 0xf model 0x40. This covers too many CPUs.

Meanwhile a respective erratum for the underlying problem was filed
(#400). This patch adds the logic to check whether erratum #400
applies to a given CPU.
Especially for CPUs where SMI/HW triggered C1e is not supported,
c1e_idle() doesn't need to be used. We can check this by looking at
the respective OSVW bit for erratum #400.

Signed-off-by: Andreas Herrmann &lt;andreas.herrmann3@amd.com&gt;
LKML-Reference: &lt;20100319110922.GA19614@alberich.amd.com&gt;
Signed-off-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
<entry>
<title>x86: Fix placement of FIX_OHCI1394_BASE</title>
<updated>2010-04-01T22:58:48Z</updated>
<author>
<name>Jan Beulich</name>
<email>JBeulich@novell.com</email>
</author>
<published>2010-03-15T10:11:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=566c0284389aa5d097356ae016cf04d3aa837195'/>
<id>urn:sha1:566c0284389aa5d097356ae016cf04d3aa837195</id>
<content type='text'>
commit ff30a0543e9a6cd732582063e7cae951cdb7acf2 upstream.

Ever for 32-bit with sufficiently high NR_CPUS, and starting
with commit 789d03f584484af85dbdc64935270c8e45f36ef7 also for
64-bit, the statically allocated early fixmap page tables were
not covering FIX_OHCI1394_BASE, leading to a boot time crash
when "ohci1394_dma=early" was used. Despite this entry not being
a permanently used one, it needs to be moved into the permanent
range since it has to be close to FIX_DBGP_BASE and
FIX_EARLYCON_MEM_BASE.

Reported-bisected-and-tested-by: Justin P. Mattock &lt;justinmattock@gmail.com&gt;
Fixes-bug: http://bugzilla.kernel.org/show_bug.cgi?id=14487
Signed-off-by: Jan Beulich &lt;jbeulich@novell.com&gt;
LKML-Reference: &lt;4B9E15D30200007800034D23@vpn.id2.novell.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@suse.de&gt;

</content>
</entry>
</feed>
