linux/arch/xtensa/kernel/head.S, branch v3.13.2

xtensa: adjust boot parameters address when INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is selected

2013-07-08T08:18:56Z

The virtual address of boot parameters chain is passed to the kernel via a2 register. Adjust it in case it is remapped during MMUv3 -> MMUv2 mapping change, i.e. when it is in the first 128M. Also fix interpretation of initrd and FDT addresses passed in the boot parameters: these are physical addresses. Cc: stable@vger.kernel.org Reported-by: Baruch Siach Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: add MMU v3 support

2013-05-09T08:07:09Z

MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB way 6: Way 6 (512 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0x00000000 0x00000000 0x01 0x03 RWX Bypass 0x20000000 0x20000000 0x01 0x03 RWX Bypass 0x40000000 0x40000000 0x01 0x03 RWX Bypass 0x60000000 0x60000000 0x01 0x03 RWX Bypass 0x80000000 0x80000000 0x01 0x03 RWX Bypass 0xa0000000 0xa0000000 0x01 0x03 RWX Bypass 0xc0000000 0xc0000000 0x01 0x03 RWX Bypass 0xe0000000 0xe0000000 0x01 0x03 RWX Bypass This patch adds remapping code at the reset vector or at the kernel _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that reconfigures MMUv3 as MMUv2: Way 5 (128 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xd0000000 0x00000000 0x01 0x07 RWX WB 0xd8000000 0x00000000 0x01 0x03 RWX Bypass Way 6 (256 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xe0000000 0xf0000000 0x01 0x07 RWX WB 0xf0000000 0xf0000000 0x01 0x03 RWX Bypass Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: fix ibreakenable register update

2013-05-09T08:07:09Z

Only set the register when there is at least one ibreak register, otherwise the build fails: arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable' for 'wsr' instruction arch/xtensa/platforms/iss/setup.c:67: Error: invalid register 'ibreakenable' for 'wsr' instruction Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: dispatch medium-priority interrupts

2013-02-24T03:12:52Z

Add support for dispatching medium-priority interrupts, that is, interrupts of priority levels 2 to EXCM_LEVEL. IRQ handling may be preempted by higher priority IRQ. Signed-off-by: Marc Gauthier Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: initialize CPENABLE SR when core has one

2012-12-19T05:10:25Z

XCHAL_CP_NUM is defined in variant/tie.h and it is not included by head.S, leaving CPENABLE register uninitialised. XCHAL_HAVE_CP is defined in variant/core.h to 1 when core has CPENABLE SR. Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: reset all timers on initialization

2012-12-19T05:10:25Z

There are XCHAL_NUM_TIMERS, reset them all. Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: initialize atomctl SR

2012-12-19T05:10:22Z

In order to use S32C1I instruction on cores with ATOMCTL SR the register must be properly initialized. Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: provide proper assembler function boundaries with ENDPROC()

2012-12-19T05:10:20Z

Use ENDPROC() to mark the end of assembler functions. Signed-off-by: Chris Zankel

xtensa: reorganize SR referencing

2012-10-16T04:48:08Z

- reference SRs by names where possible, not by numbers; - get rid of __stringify around SR names where possible; - remove unneeded SR names from asm/regs.h; - add SREG_ prefix to remaining SR names; Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: Fixes due to bss boundary symbol name changes.

2010-05-02T06:05:29Z

The bss start and end symbols have changed to __bss_start and __bss_stop. Signed-off-by: Chris Zankel