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<title>linux/arch/tile/kernel/single_step.c, branch v3.13</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch/tile/kernel/single_step.c?h=v3.13</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch/tile/kernel/single_step.c?h=v3.13'/>
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<updated>2013-09-03T18:53:29Z</updated>
<entry>
<title>tile: remove support for TILE64</title>
<updated>2013-09-03T18:53:29Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-15T20:23:24Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=d7c9661115fd23b4dabb710b3080dd9919dfa891'/>
<id>urn:sha1:d7c9661115fd23b4dabb710b3080dd9919dfa891</id>
<content type='text'>
This chip is no longer being actively developed for (it was superceded
by the TILEPro64 in 2008), and in any case the existing compiler and
toolchain in the community do not support it.  It's unlikely that the
kernel works with TILE64 at this point as the configuration has not been
tested in years.  The support is also awkward as it requires maintaining
a significant number of ifdefs.  So, just remove it altogether.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: fast-path unaligned memory access for tilegx</title>
<updated>2013-08-13T20:04:10Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-06T20:04:13Z</published>
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<id>urn:sha1:2f9ac29eec71a696cb0dcc5fb82c0f8d4dac28c9</id>
<content type='text'>
This change enables unaligned userspace memory access via a kernel
fast path on tilegx.  The kernel tracks user PC/instruction pairs
per-thread using a direct-mapped cache in userspace.  The cache
maps those PC/instruction pairs to JIT'ed instruction sequences that
load or store using byte-wide load store intructions and then
synthesize 2-, 4- or 8-byte load or store results.  Once an
instruction has been seen to generate an unaligned access once,
subsequent hits on that instruction typically require overhead
of only around 50 cycles if cache and TLB is hot.

We support the prctl() PR_GET_UNALIGN / PR_SET_UNALIGN sys call to
enable or disable unaligned fixups on a per-process basis.

To do this we pull some of the tilepro unaligned support out of the
single_step.c file; tilepro uses instruction disassembly for both
single-step and unaligned access support.  Since tilegx actually has
hardware singlestep support, though, it's cleaner to keep the tilegx
unaligned access code in a separate file.  While we're at it,
properly rename the tilepro-specific types, etc., to have tilepro
suffixes instead of generic tile suffixes.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: support building big-endian kernel</title>
<updated>2012-05-25T16:48:22Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-03-29T17:30:31Z</published>
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<id>urn:sha1:1efea40d4172a2a475ccb29b59d6221e9d0c174b</id>
<content type='text'>
The toolchain supports big-endian mode now, so add support for building
the kernel to run big-endian as well.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>VM: add "vm_mmap()" helper function</title>
<updated>2012-04-21T00:29:13Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2012-04-21T00:13:58Z</published>
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<id>urn:sha1:6be5ceb02e98eaf6cfc4f8b12a896d04023f340d</id>
<content type='text'>
This continues the theme started with vm_brk() and vm_munmap():
vm_mmap() does the same thing as do_mmap(), but additionally does the
required VM locking.

This uninlines (and rewrites it to be clearer) do_mmap(), which sadly
duplicates it in mm/mmap.c and mm/nommu.c.  But that way we don't have
to export our internal do_mmap_pgoff() function.

Some day we hopefully don't have to export do_mmap() either, if all
modular users can become the simpler vm_mmap() instead.  We're actually
very close to that already, with the notable exception of the (broken)
use in i810, and a couple of stragglers in binfmt_elf.

Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>arch/tile: return SIGBUS for addresses that are unaligned AND invalid</title>
<updated>2012-04-02T16:13:56Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-03-30T20:24:41Z</published>
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<id>urn:sha1:cdd8e16feba87a3fc2bb1885d36f895a2a3288bf</id>
<content type='text'>
Previously we were returning SIGSEGV in this case.  It seems cleaner
to return SIGBUS since the hardware figures out alignment traps
before TLB violations, so SIGBUS is the "more correct" signal.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>Disintegrate asm/system.h for Tile</title>
<updated>2012-03-28T17:30:03Z</updated>
<author>
<name>David Howells</name>
<email>dhowells@redhat.com</email>
</author>
<published>2012-03-28T17:30:03Z</published>
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<id>urn:sha1:bd119c69239322caafdb64517a806037d0d0c70a</id>
<content type='text'>
Disintegrate asm/system.h for Tile.

Signed-off-by: David Howells &lt;dhowells@redhat.com&gt;
Acked-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: factor out &lt;arch/opcode.h&gt; header</title>
<updated>2011-11-03T20:58:54Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2011-11-03T03:02:17Z</published>
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<id>urn:sha1:eb7c792da5afa3b9ec3e802c30952f82d2e9722b</id>
<content type='text'>
The kernel code was using some &lt;asm&gt; headers that included a mix
of hardware-specific information (typically found in Tilera &lt;arch&gt;
headers) and structures, enums, and function declarations supporting
the disassembly function of the tile-desc.c sources.

This change refactors that code so that a hardware-specific, but
OS- and application-agnostic header, is created: &lt;arch/opcode.h&gt;.
This header is then exported to userspace along with the other
&lt;arch&gt; headers and can be used to build userspace code; in particular,
it is used by glibc as part of implementing the backtrace() function.

The new header, together with a header that specifically describes
the disassembly code (&lt;asm/tile-desc.h&gt; with _32 and _64 variants),
replaces the old &lt;asm/opcode-tile*.h&gt; and &lt;asm/opcode_constants*.h&gt;
headers.

As part of this change, we are also renaming the 32-bit constants
from TILE_xxx to TILEPRO_xxx to better reflect the fact that they
are specific to the TILEPro architecture, and not to TILE-Gx
and any successor "tile" architecture chips.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: support signal "exception-trace" hook</title>
<updated>2011-05-20T02:55:59Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2011-05-16T18:23:44Z</published>
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<id>urn:sha1:571d76acdab95876aeff869ab6449f826c23aa43</id>
<content type='text'>
This change adds support for /proc/sys/debug/exception-trace to tile.
Like x86 and sparc, by default it is set to "1", generating a one-line
printk whenever a user process crashes.  By setting it to "2", we get
a much more complete userspace diagnostic at crash time, including
a user-space backtrace, register dump, and memory dump around the
address of the crash.

Some vestiges of the Tilera-internal version of this support are
removed with this patch (the show_crashinfo variable and the
arch_coredump_signal function).  We retain a "crashinfo" boot parameter
which allows you to set the boot-time value of exception-trace.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: support TIF_NOTIFY_RESUME</title>
<updated>2011-05-02T22:53:35Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2011-05-02T18:50:06Z</published>
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<id>urn:sha1:313ce674d3cbc2d48ed34a9462427920ac54f4ad</id>
<content type='text'>
This support is required for CONFIG_KEYS, NFSv4 kernel DNS, etc.
The change is slightly more complex than the minimal thing, since
I took advantage of having to go into the assembly code to just
move a bunch of stuff into C code: specifically, the schedule(),
do_async_page_fault(), do_signal(), and single_step_once() support,
in addition to the TIF_NOTIFY_RESUME support.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: bug fix: exec'ed task thought it was still single-stepping</title>
<updated>2011-03-01T21:19:58Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2011-02-28T18:08:32Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=04f7a3f12e10032ee3d44df1a509dbf5b2001fce'/>
<id>urn:sha1:04f7a3f12e10032ee3d44df1a509dbf5b2001fce</id>
<content type='text'>
To handle single-step, tile mmap's a page of memory in the process
space for each thread and uses it to construct a version of the
instruction that we want to single step.  If the process exec's,
though, we lose that mapping, and the kernel needs to be aware that
it will need to recreate it if the exec'ed process than tries to
single-step as well.

Also correct some int32_t to s32 for better kernel style.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
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