<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/tile/kernel/setup.c, branch v3.13</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch/tile/kernel/setup.c?h=v3.13</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch/tile/kernel/setup.c?h=v3.13'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2013-09-13T15:15:24Z</updated>
<entry>
<title>tile: remove HUGE_VMAP dead code</title>
<updated>2013-09-13T15:15:24Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-11T17:57:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=4b12909fd137d9a236e4b5c76e0d4b44c2b7f49f'/>
<id>urn:sha1:4b12909fd137d9a236e4b5c76e0d4b44c2b7f49f</id>
<content type='text'>
A config option to allow a variant vmap() using huge pages that was never
upstreamed had some bits of code related to it scattered around the tile
architecture; the config option was removed downstream and this commit
cleans up the scattered evidence of it from the upstream as well.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile</title>
<updated>2013-09-06T18:14:33Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-09-06T18:14:33Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=4de9ad9bc08b4953fc03336ad38908496e2f8826'/>
<id>urn:sha1:4de9ad9bc08b4953fc03336ad38908496e2f8826</id>
<content type='text'>
Pull Tile arch updates from Chris Metcalf:
 "These changes bring in a bunch of new functionality that has been
  maintained internally at Tilera over the last year, plus other stray
  bits of work that I've taken into the tile tree from other folks.

  The changes include some PCI root complex work, interrupt-driven
  console support, support for performing fast-path unaligned data
  fixups by kernel-based JIT code generation, CONFIG_PREEMPT support,
  vDSO support for gettimeofday(), a serial driver for the tilegx
  on-chip UART, KGDB support, more optimized string routines, support
  for ftrace and kprobes, improved ASLR, and many bug fixes.

  We also remove support for the old TILE64 chip, which is no longer
  buildable"

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (85 commits)
  tile: refresh tile defconfig files
  tile: rework &lt;asm/cmpxchg.h&gt;
  tile PCI RC: make default consistent DMA mask 32-bit
  tile: add null check for kzalloc in tile/kernel/setup.c
  tile: make __write_once a synonym for __read_mostly
  tile: remove support for TILE64
  tile: use asm-generic/bitops/builtin-*.h
  tile: eliminate no-op "noatomichash" boot argument
  tile: use standard tile_bundle_bits type in traps.c
  tile: simplify code referencing hypervisor API addresses
  tile: change &lt;asm/system.h&gt; to &lt;asm/switch_to.h&gt; in comments
  tile: mark pcibios_init() as __init
  tile: check for correct compiler earlier in asm-offsets.c
  tile: use standard 'generic-y' model for &lt;asm/hw_irq.h&gt;
  tile: use asm-generic version of &lt;asm/local64.h&gt;
  tile PCI RC: add comment about "PCI hole" problem
  tile: remove DEBUG_EXTRA_FLAGS kernel config option
  tile: add virt_to_kpte() API and clean up and document behavior
  tile: support FRAME_POINTER
  tile: support reporting Tilera hypervisor statistics
  ...
</content>
</entry>
<entry>
<title>tile: add null check for kzalloc in tile/kernel/setup.c</title>
<updated>2013-09-03T18:53:34Z</updated>
<author>
<name>Wang Sheng-Hui</name>
<email>shhuiw@gmail.com</email>
</author>
<published>2013-08-22T01:49:42Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=6d715790ef6b5b903779a14d995ce3d9e680bec0'/>
<id>urn:sha1:6d715790ef6b5b903779a14d995ce3d9e680bec0</id>
<content type='text'>
Should check the return value of kzalloc first to avoid the null pointer.
Then can dereference the non-null pointer to access the fields of struct
resource.

Signed-off-by: Wang Sheng-Hui &lt;shhuiw@gmail.com&gt;
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: remove support for TILE64</title>
<updated>2013-09-03T18:53:29Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-15T20:23:24Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=d7c9661115fd23b4dabb710b3080dd9919dfa891'/>
<id>urn:sha1:d7c9661115fd23b4dabb710b3080dd9919dfa891</id>
<content type='text'>
This chip is no longer being actively developed for (it was superceded
by the TILEPro64 in 2008), and in any case the existing compiler and
toolchain in the community do not support it.  It's unlikely that the
kernel works with TILE64 at this point as the configuration has not been
tested in years.  The support is also awkward as it requires maintaining
a significant number of ifdefs.  So, just remove it altogether.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: add virt_to_kpte() API and clean up and document behavior</title>
<updated>2013-09-03T18:52:13Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-12T19:08:09Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=640710a33b54de8d90ae140ef633ed0feba76a75'/>
<id>urn:sha1:640710a33b54de8d90ae140ef633ed0feba76a75</id>
<content type='text'>
We use virt_to_pte(NULL, va) a lot, which isn't very obvious.
I added virt_to_kpte(va) as a more obvious wrapper function,
that also validates the va as being a kernel adddress.

And, I fixed the semantics of virt_to_pte() so that we handle
the pud and pmd the same way, and we now document the fact that
we handle the final pte level differently.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: parameterize VA and PA space more cleanly</title>
<updated>2013-09-03T18:47:34Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-03T18:41:36Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=acbde1db294932623aad15dd8cc6e37b28340f26'/>
<id>urn:sha1:acbde1db294932623aad15dd8cc6e37b28340f26</id>
<content type='text'>
The existing code relied on the hardware definition (&lt;arch/chip.h&gt;)
to specify how much VA and PA space was available.  It's convenient
to allow customizing this for some configurations, so provide symbols
MAX_PA_WIDTH and MAX_VA_WIDTH in &lt;asm/page.h&gt; that can be modified
if desired.

Additionally, move away from the MEM_XX_INTRPT nomenclature to
define the start of various regions within the VA space.  In fact
the cleaner symbol is, for example, MEM_SV_START, to indicate the
start of the area used for supervisor code; the actual address of the
interrupt vectors is not as important, and can be changed if desired.
As part of this change, convert from "intrpt1" nomenclature (which
built in the old privilege-level 1 model) to a simple "intrpt".

Also strip out some tilepro-specific code supporting modifying the
PL the kernel could run at, since we don't actually support using
different PLs in tilepro, only tilegx.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: allow "initrd" boot argument for kexec</title>
<updated>2013-08-30T15:56:30Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-09T20:04:34Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=6f0142d501b35468d910b9f36b6853dbd8dc5ad5'/>
<id>urn:sha1:6f0142d501b35468d910b9f36b6853dbd8dc5ad5</id>
<content type='text'>
This enables support for "kexec --initrd" for tile.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: support "memmap" boot parameter</title>
<updated>2013-08-12T18:46:43Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-06T18:29:59Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=77f8c740d1a4947afb7493e7aafdd977e6d7939c'/>
<id>urn:sha1:77f8c740d1a4947afb7493e7aafdd977e6d7939c</id>
<content type='text'>
This change adds support for the "memmap" boot parameter similar
to what x86 provides.  The tile version supports "memmap=1G$5G",
for example, as a way to reserve a 1 GB range starting at PA 5GB.
The memory is reserved via bootmem during startup, and we create a
suitable "struct resource" marked as "Reserved" so you can see the
range reported by /proc/iomem.  Up to 64 such regions can currently
be reserved on the boot command line.

We do not support the x86 options "memmap=nn@ss" (force some memory
to be available at the given address) since it's pointless to try to
have Linux use memory the Tilera hypervisor hasn't given it.  We do
not support "memmap=nn#ss" to add an ACPI range for later processing,
since we don't support ACPI.  We do not support "memmap=exactmap"
since we don't support reading the e820 information from the BIOS
like x86 does.  I did add support for "memmap=nn" (and the synonym
"mem=nn") which cap the highest PA value at "nn"; these are both
just a synonym for the existing tile boot option "maxmem".

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile PCI RC: tilepro conflict with PCI and RAM addresses</title>
<updated>2013-08-05T20:12:51Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-02T20:18:58Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=523c178edf45fe04d61aa99ac496bc7494b99810'/>
<id>urn:sha1:523c178edf45fe04d61aa99ac496bc7494b99810</id>
<content type='text'>
Fix a bug in the tilepro PCI resource allocation code that could make
the bootmem allocator unhappy if 4GB is installed on mshim 0.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: delete __cpuinit usage from all tile files</title>
<updated>2013-07-14T23:36:54Z</updated>
<author>
<name>Paul Gortmaker</name>
<email>paul.gortmaker@windriver.com</email>
</author>
<published>2013-06-18T21:28:07Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=18f894c145e8515c26da09dd95e06d6b1158775c'/>
<id>urn:sha1:18f894c145e8515c26da09dd95e06d6b1158775c</id>
<content type='text'>
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications.  For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out.  Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit  -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings.  In any case, they are temporary and harmless.

This removes all the arch/tile uses of the __cpuinit macros from
all C files.  Currently tile does not have any __CPUINIT used in
assembly files.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Signed-off-by: Paul Gortmaker &lt;paul.gortmaker@windriver.com&gt;
</content>
</entry>
</feed>
