<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/tile/include, branch v3.13</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch/tile/include?h=v3.13</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch/tile/include?h=v3.13'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2013-11-13T19:21:47Z</updated>
<entry>
<title>preempt: Make PREEMPT_ACTIVE generic</title>
<updated>2013-11-13T19:21:47Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2013-09-17T18:53:09Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=00d1a39e69d5afa7523dad515a05b21abd17c389'/>
<id>urn:sha1:00d1a39e69d5afa7523dad515a05b21abd17c389</id>
<content type='text'>
No point in having this bit defined by architecture.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Peter Zijlstra &lt;peterz@infradead.org&gt;
Link: http://lkml.kernel.org/r/20130917183629.090698799@linutronix.de
</content>
</entry>
<entry>
<title>hardirq: Make hardirq bits generic</title>
<updated>2013-11-13T19:21:46Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2013-09-17T18:53:05Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=54197e43a4a9a0f3fc406d72d9815754e84fab1e'/>
<id>urn:sha1:54197e43a4a9a0f3fc406d72d9815754e84fab1e</id>
<content type='text'>
There is no reason for per arch hardirq bits. Make them all generic

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Peter Zijlstra &lt;peterz@infradead.org&gt;
Link: http://lkml.kernel.org/r/20130917183628.534494408@linutronix.de
</content>
</entry>
<entry>
<title>Merge branch 'core/urgent' into sched/core</title>
<updated>2013-10-11T05:39:37Z</updated>
<author>
<name>Ingo Molnar</name>
<email>mingo@kernel.org</email>
</author>
<published>2013-10-11T05:39:37Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=ec0ad3d01f99d5e5b56a99a58f7003b99250dc65'/>
<id>urn:sha1:ec0ad3d01f99d5e5b56a99a58f7003b99250dc65</id>
<content type='text'>
Merge in asm goto fix, to be able to apply the asm/rmwcc.h fix.

Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>tile: use a more conservative __my_cpu_offset in CONFIG_PREEMPT</title>
<updated>2013-09-30T14:34:41Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-26T17:24:53Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=f862eefec0b68e099a9fa58d3761ffb10bad97e1'/>
<id>urn:sha1:f862eefec0b68e099a9fa58d3761ffb10bad97e1</id>
<content type='text'>
It turns out the kernel relies on barrier() to force a reload of the
percpu offset value.  Since we can't easily modify the definition of
barrier() to include "tp" as an output register, we instead provide a
definition of __my_cpu_offset as extended assembly that includes a fake
stack read to hazard against barrier(), forcing gcc to know that it
must reread "tp" and recompute anything based on "tp" after a barrier.

This fixes observed hangs in the slub allocator when we are looping
on a percpu cmpxchg_double.

A similar fix for ARMv7 was made in June in change 509eb76ebf97.

Cc: stable@vger.kernel.org
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: include: asm: use 'long long' instead of 'u64' for atomic64_t and its related functions</title>
<updated>2013-09-27T20:08:56Z</updated>
<author>
<name>Chen Gang</name>
<email>gang.chen@asianux.com</email>
</author>
<published>2013-09-25T04:14:08Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=b924a69067b00d3121debae5a738fb0bcbbbb03c'/>
<id>urn:sha1:b924a69067b00d3121debae5a738fb0bcbbbb03c</id>
<content type='text'>
atomic* value is signed value, and atomic* functions need also process
signed value (parameter value, and return value), so use 'long long'
instead of 'u64'.

After replacement, it will also fix a bug for atomic64_add_negative():
"u64 is never less than 0".

The modifications are:

  in vim, use "1,% s/\&lt;u64\&gt;/long long/g" command.
  remove redundant '__aligned(8)'.
  be sure of 80 (and macro '\') columns limitation after replacement.

Signed-off-by: Chen Gang &lt;gang.chen@asianux.com&gt;
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt; [re-instated const cast]
</content>
</entry>
<entry>
<title>sched, arch: Create asm/preempt.h</title>
<updated>2013-09-25T12:07:50Z</updated>
<author>
<name>Peter Zijlstra</name>
<email>peterz@infradead.org</email>
</author>
<published>2013-08-14T12:55:40Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=a787870924dbd6f321661e06d4ec1c7a408c9ccf'/>
<id>urn:sha1:a787870924dbd6f321661e06d4ec1c7a408c9ccf</id>
<content type='text'>
In order to prepare to per-arch implementations of preempt_count move
the required bits into an asm-generic header and use this for all
archs.

Signed-off-by: Peter Zijlstra &lt;peterz@infradead.org&gt;
Link: http://lkml.kernel.org/n/tip-h5j0c1r3e3fk015m30h8f1zx@git.kernel.org
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>tile: &lt;arch/&gt; header updates from upstream</title>
<updated>2013-09-16T19:47:26Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-16T18:18:21Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=88e2692a4dff0d1f80e9761ade3db2ea59206c1e'/>
<id>urn:sha1:88e2692a4dff0d1f80e9761ade3db2ea59206c1e</id>
<content type='text'>
The hardware architecture descriptor headers have been updated, in
particular to reflect some larger MMIO fields on the mPIPE shims for
controlling the network hardware, from the recent Gx72 release.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: improve gxio iorpc autogenerated code style</title>
<updated>2013-09-16T19:47:20Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-16T17:52:45Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=126eb08820a2c97c10ea58e73a544c2f075d59a7'/>
<id>urn:sha1:126eb08820a2c97c10ea58e73a544c2f075d59a7</id>
<content type='text'>
Fix some whitespace style issues in some auto-generated files.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: remove HUGE_VMAP dead code</title>
<updated>2013-09-13T15:15:24Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-11T17:57:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=4b12909fd137d9a236e4b5c76e0d4b44c2b7f49f'/>
<id>urn:sha1:4b12909fd137d9a236e4b5c76e0d4b44c2b7f49f</id>
<content type='text'>
A config option to allow a variant vmap() using huge pages that was never
upstreamed had some bits of code related to it scattered around the tile
architecture; the config option was removed downstream and this commit
cleans up the scattered evidence of it from the upstream as well.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile</title>
<updated>2013-09-06T18:14:33Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2013-09-06T18:14:33Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=4de9ad9bc08b4953fc03336ad38908496e2f8826'/>
<id>urn:sha1:4de9ad9bc08b4953fc03336ad38908496e2f8826</id>
<content type='text'>
Pull Tile arch updates from Chris Metcalf:
 "These changes bring in a bunch of new functionality that has been
  maintained internally at Tilera over the last year, plus other stray
  bits of work that I've taken into the tile tree from other folks.

  The changes include some PCI root complex work, interrupt-driven
  console support, support for performing fast-path unaligned data
  fixups by kernel-based JIT code generation, CONFIG_PREEMPT support,
  vDSO support for gettimeofday(), a serial driver for the tilegx
  on-chip UART, KGDB support, more optimized string routines, support
  for ftrace and kprobes, improved ASLR, and many bug fixes.

  We also remove support for the old TILE64 chip, which is no longer
  buildable"

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (85 commits)
  tile: refresh tile defconfig files
  tile: rework &lt;asm/cmpxchg.h&gt;
  tile PCI RC: make default consistent DMA mask 32-bit
  tile: add null check for kzalloc in tile/kernel/setup.c
  tile: make __write_once a synonym for __read_mostly
  tile: remove support for TILE64
  tile: use asm-generic/bitops/builtin-*.h
  tile: eliminate no-op "noatomichash" boot argument
  tile: use standard tile_bundle_bits type in traps.c
  tile: simplify code referencing hypervisor API addresses
  tile: change &lt;asm/system.h&gt; to &lt;asm/switch_to.h&gt; in comments
  tile: mark pcibios_init() as __init
  tile: check for correct compiler earlier in asm-offsets.c
  tile: use standard 'generic-y' model for &lt;asm/hw_irq.h&gt;
  tile: use asm-generic version of &lt;asm/local64.h&gt;
  tile PCI RC: add comment about "PCI hole" problem
  tile: remove DEBUG_EXTRA_FLAGS kernel config option
  tile: add virt_to_kpte() API and clean up and document behavior
  tile: support FRAME_POINTER
  tile: support reporting Tilera hypervisor statistics
  ...
</content>
</entry>
</feed>
