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<title>linux/arch/tile/include/asm/processor.h, branch v3.13</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch/tile/include/asm/processor.h?h=v3.13</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch/tile/include/asm/processor.h?h=v3.13'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2013-09-03T18:53:29Z</updated>
<entry>
<title>tile: remove support for TILE64</title>
<updated>2013-09-03T18:53:29Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-15T20:23:24Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=d7c9661115fd23b4dabb710b3080dd9919dfa891'/>
<id>urn:sha1:d7c9661115fd23b4dabb710b3080dd9919dfa891</id>
<content type='text'>
This chip is no longer being actively developed for (it was superceded
by the TILEPro64 in 2008), and in any case the existing compiler and
toolchain in the community do not support it.  It's unlikely that the
kernel works with TILE64 at this point as the configuration has not been
tested in years.  The support is also awkward as it requires maintaining
a significant number of ifdefs.  So, just remove it altogether.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: parameterize VA and PA space more cleanly</title>
<updated>2013-09-03T18:47:34Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-03T18:41:36Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=acbde1db294932623aad15dd8cc6e37b28340f26'/>
<id>urn:sha1:acbde1db294932623aad15dd8cc6e37b28340f26</id>
<content type='text'>
The existing code relied on the hardware definition (&lt;arch/chip.h&gt;)
to specify how much VA and PA space was available.  It's convenient
to allow customizing this for some configurations, so provide symbols
MAX_PA_WIDTH and MAX_VA_WIDTH in &lt;asm/page.h&gt; that can be modified
if desired.

Additionally, move away from the MEM_XX_INTRPT nomenclature to
define the start of various regions within the VA space.  In fact
the cleaner symbol is, for example, MEM_SV_START, to indicate the
start of the area used for supervisor code; the actual address of the
interrupt vectors is not as important, and can be changed if desired.
As part of this change, convert from "intrpt1" nomenclature (which
built in the old privilege-level 1 model) to a simple "intrpt".

Also strip out some tilepro-specific code supporting modifying the
PL the kernel could run at, since we don't actually support using
different PLs in tilepro, only tilegx.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: don't assume user privilege is zero</title>
<updated>2013-09-03T18:45:52Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-09-03T18:45:52Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=051168df528fe4456d63f5f65b041c147c26fe97'/>
<id>urn:sha1:051168df528fe4456d63f5f65b041c147c26fe97</id>
<content type='text'>
Technically, user privilege is anything less than kernel
privilege.  We modify the existing user_mode() macro to have
this semantic (and use it in a couple of places it wasn't being
used before), and add an IS_KERNEL_EX1() macro to the assembly
code as well.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tilegx: change how we find the kernel stack</title>
<updated>2013-08-30T15:56:58Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-10T16:35:02Z</published>
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<id>urn:sha1:35f059761c5ac313d13372fe3cdaa41bce3d0dbf</id>
<content type='text'>
Previously, we used a special-purpose register (SPR_SYSTEM_SAVE_K_0)
to hold the CPU number and the top of the current kernel stack
by using the low bits to hold the CPU number, and using the high
bits to hold the address of the page just above where we'd want
the kernel stack to be.  That way we could initialize a new SP
when first entering the kernel by just masking the SPR value and
subtracting a couple of words.

However, it's actually more useful to be able to place an arbitrary
kernel-top value in the SPR.  This allows us to create a new stack
context (e.g. for virtualization) with an arbitrary top-of-stack VA.
To make this work, we now store the CPU number in the high bits,
above the highest legal VA bit (42 bits in the current tilegx
microarchitecture).  The full 42 bits are thus available to store the
top of stack value.  Getting the current cpu (a relatively common
operation) is still fast; it's now a shift rather than a mask.

We make this change only for tilegx, since tilepro has too few SPR
bits to do this, and we don't need this support on tilepro anyway.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: implement gettimeofday() via vDSO</title>
<updated>2013-08-13T20:26:21Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-07T19:33:32Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=4a556f4f56da3110b27e265b79f0e7582115445c'/>
<id>urn:sha1:4a556f4f56da3110b27e265b79f0e7582115445c</id>
<content type='text'>
This change creates the framework for vDSO calls, makes the existing
rt_sigreturn() mechanism use it, and adds a fast gettimeofday().
Now that we need to expose the vDSO address to userspace, we add
AT_SYSINFO_EHDR to the set of aux entries provided to userspace.
(You can disable any extra vDSO support by booting with vdso=0,
but the rt_sigreturn vDSO page will still be provided.)

Note that glibc has supported the tile vDSO since release 2.17.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: avoid recursive backtrace faults</title>
<updated>2013-08-13T20:04:14Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-06T20:10:23Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=3ef23111546df9e9dab2e2befb412a9563db0628'/>
<id>urn:sha1:3ef23111546df9e9dab2e2befb412a9563db0628</id>
<content type='text'>
This change adds support for avoiding recursive backtracer crashes;
we haven't seen this in practice other than when things are seriously
corrupt, but it may help avoid losing the root cause of a crash.

Also, don't abort kernel backtracers for invalid userspace PC's.
If we do, we lose the ability to backtrace through a userspace
call to a bad address above PAGE_OFFSET, even though that it can
be perfectly reasonable to continue the backtrace in such a case.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: fast-path unaligned memory access for tilegx</title>
<updated>2013-08-13T20:04:10Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2013-08-06T20:04:13Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=2f9ac29eec71a696cb0dcc5fb82c0f8d4dac28c9'/>
<id>urn:sha1:2f9ac29eec71a696cb0dcc5fb82c0f8d4dac28c9</id>
<content type='text'>
This change enables unaligned userspace memory access via a kernel
fast path on tilegx.  The kernel tracks user PC/instruction pairs
per-thread using a direct-mapped cache in userspace.  The cache
maps those PC/instruction pairs to JIT'ed instruction sequences that
load or store using byte-wide load store intructions and then
synthesize 2-, 4- or 8-byte load or store results.  Once an
instruction has been seen to generate an unaligned access once,
subsequent hits on that instruction typically require overhead
of only around 50 cycles if cache and TLB is hot.

We support the prctl() PR_GET_UNALIGN / PR_SET_UNALIGN sys call to
enable or disable unaligned fixups on a per-process basis.

To do this we pull some of the tilepro unaligned support out of the
single_step.c file; tilepro uses instruction disassembly for both
single-step and unaligned access support.  Since tilegx actually has
hardware singlestep support, though, it's cleaner to keep the tilegx
unaligned access code in a separate file.  While we're at it,
properly rename the tilepro-specific types, etc., to have tilepro
suffixes instead of generic tile suffixes.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>sched: Rename sched.c as sched/core.c in comments and Documentation</title>
<updated>2013-06-19T10:58:42Z</updated>
<author>
<name>Viresh Kumar</name>
<email>viresh.kumar@linaro.org</email>
</author>
<published>2013-06-04T07:40:24Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=0a0fca9d832b704f116a25badd1ca8c16771dcac'/>
<id>urn:sha1:0a0fca9d832b704f116a25badd1ca8c16771dcac</id>
<content type='text'>
Most of the stuff from kernel/sched.c was moved to kernel/sched/core.c long time
back and the comments/Documentation never got updated.

I figured it out when I was going through sched-domains.txt and so thought of
fixing it globally.

I haven't crossed check if the stuff that is referenced in sched/core.c by all
these files is still present and hasn't changed as that wasn't the motive behind
this patch.

Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Peter Zijlstra &lt;peterz@infradead.org&gt;
Link: http://lkml.kernel.org/r/cdff76a265326ab8d71922a1db5be599f20aad45.1370329560.git.viresh.kumar@linaro.org
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>kill stray kernel_thread() garbage</title>
<updated>2012-11-29T02:53:36Z</updated>
<author>
<name>Al Viro</name>
<email>viro@zeniv.linux.org.uk</email>
</author>
<published>2012-10-21T01:42:37Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=910cdc553a324d3df56b73c84cdef20836817d52'/>
<id>urn:sha1:910cdc553a324d3df56b73c84cdef20836817d52</id>
<content type='text'>
Signed-off-by: Al Viro &lt;viro@zeniv.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>tile: switch to generic sys_execve()</title>
<updated>2012-10-23T17:40:12Z</updated>
<author>
<name>Al Viro</name>
<email>viro@zeniv.linux.org.uk</email>
</author>
<published>2012-10-20T17:14:08Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=530550651fdfd548d25b6bd5ff4607803540508b'/>
<id>urn:sha1:530550651fdfd548d25b6bd5ff4607803540508b</id>
<content type='text'>
Acked-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Signed-off-by: Al Viro &lt;viro@zeniv.linux.org.uk&gt;
</content>
</entry>
</feed>
