<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/tile/include/asm/module.h, branch v3.13</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch/tile/include/asm/module.h?h=v3.13</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch/tile/include/asm/module.h?h=v3.13'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2012-05-25T16:48:24Z</updated>
<entry>
<title>arch/tile: Allow tilegx to build with either 16K or 64K page size</title>
<updated>2012-05-25T16:48:24Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-03-29T17:58:43Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=d5d14ed6f2db7287a5088e1350cf422bf72140b3'/>
<id>urn:sha1:d5d14ed6f2db7287a5088e1350cf422bf72140b3</id>
<content type='text'>
This change introduces new flags for the hv_install_context()
API that passes a page table pointer to the hypervisor.  Clients
can explicitly request 4K, 16K, or 64K small pages when they
install a new context.  In practice, the page size is fixed at
kernel compile time and the same size is always requested every
time a new page table is installed.

The &lt;hv/hypervisor.h&gt; header changes so that it provides more abstract
macros for managing "page" things like PFNs and page tables.  For
example there is now a HV_DEFAULT_PAGE_SIZE_SMALL instead of the old
HV_PAGE_SIZE_SMALL.  The various PFN routines have been eliminated and
only PA- or PTFN-based ones remain (since PTFNs are always expressed
in fixed 2KB "page" size).  The page-table management macros are
renamed with a leading underscore and take page-size arguments with
the presumption that clients will use those macros in some single
place to provide the "real" macros they will use themselves.

I happened to notice the old hv_set_caching() API was totally broken
(it assumed 4KB pages) so I changed it so it would nominally work
correctly with other page sizes.

Tag modules with the page size so you can't load a module built with
a conflicting page size.  (And add a test for SMP while we're at it.)

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: use generic-y format for one-line asm-generic headers</title>
<updated>2011-06-03T21:36:18Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2011-06-03T21:36:18Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=2c007a9d8cb018a3ce2106342f2aff2abca2a3bd'/>
<id>urn:sha1:2c007a9d8cb018a3ce2106342f2aff2abca2a3bd</id>
<content type='text'>
This lets us remove a lot of one-line wrapper header files.
See commit d8ecc5cd8e227bc318513b5306ae88a474b8886d for context.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: core support for Tilera 32-bit chips.</title>
<updated>2010-06-04T21:11:18Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-05-29T03:09:12Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=867e359b97c970a60626d5d76bbe2a8fadbf38fb'/>
<id>urn:sha1:867e359b97c970a60626d5d76bbe2a8fadbf38fb</id>
<content type='text'>
This change is the core kernel support for TILEPro and TILE64 chips.
No driver support (except the console driver) is included yet.

This includes the relevant Linux headers in asm/; the low-level
low-level "Tile architecture" headers in arch/, which are
shared with the hypervisor, etc., and are build-system agnostic;
and the relevant hypervisor headers in hv/.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: FUJITA Tomonori &lt;fujita.tomonori@lab.ntt.co.jp&gt;
Reviewed-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
</feed>
