<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/tile/include/asm/cache.h, branch v3.0.43</title>
<subtitle>Linux kernel source tree</subtitle>
<id>https://git.amat.us/linux/atom/arch/tile/include/asm/cache.h?h=v3.0.43</id>
<link rel='self' href='https://git.amat.us/linux/atom/arch/tile/include/asm/cache.h?h=v3.0.43'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/'/>
<updated>2011-03-01T21:18:52Z</updated>
<entry>
<title>arch/tile: catch up with section naming convention in 2.6.35</title>
<updated>2011-03-01T21:18:52Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2011-02-27T23:52:24Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=2cb82400719e085a3c226cf7cce8950208f09a06'/>
<id>urn:sha1:2cb82400719e085a3c226cf7cce8950208f09a06</id>
<content type='text'>
The convention changed to, e.g., ".data..page_aligned".  This commit
fixes the places in the tile architecture that were still using the
old convention.  One tile-specific section (.init.page) was dropped
in favor of just using an "aligned" attribute.

Sam Ravnborg &lt;sam@ravnborg.org&gt; pointed out __PAGE_ALIGNED_BSS, etc.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: rename ARCH_KMALLOC_MINALIGN to ARCH_DMA_MINALIGN</title>
<updated>2010-08-15T15:05:33Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-08-14T00:43:39Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=b3ae98ab8217a8621859e1d9cbf3ee6c4c19533b'/>
<id>urn:sha1:b3ae98ab8217a8621859e1d9cbf3ee6c4c19533b</id>
<content type='text'>
See commit a6eb9fe105d5de0053b261148cee56c94b4720ca.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Acked-by: FUJITA Tomonori &lt;fujita.tomonori@lab.ntt.co.jp&gt;
</content>
</entry>
<entry>
<title>arch/tile: catch up on various minor cleanups.</title>
<updated>2010-07-06T17:42:15Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-07-02T18:19:35Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=ef06f55a5c936a395f3ee2e1237bbebdb4396c65'/>
<id>urn:sha1:ef06f55a5c936a395f3ee2e1237bbebdb4396c65</id>
<content type='text'>
None of these changes fix any actual bugs, but are just various cleanups
that fell out along the way.  In particular, some unused #defines and
includes are removed, PREFETCH_STRIDE is added (the default is right for
our shipping chips, but wrong for our next generation), our tile-specific
prefetching code is removed so the (identical) generic prefetching code
can be used instead, a comment is fixed to be proper GPL and not just a
"paste GPL here" token, a "//" comment is converted to "/* */", etc.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>tile: set ARCH_KMALLOC_MINALIGN</title>
<updated>2010-07-06T17:42:04Z</updated>
<author>
<name>FUJITA Tomonori</name>
<email>fujita.tomonori@lab.ntt.co.jp</email>
</author>
<published>2010-06-30T02:10:08Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=c6673cb54d191dd42935a61fcb0c452a4753fb23'/>
<id>urn:sha1:c6673cb54d191dd42935a61fcb0c452a4753fb23</id>
<content type='text'>
Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe:
the buffer doesn't share a cache with the others.

Signed-off-by: FUJITA Tomonori &lt;fujita.tomonori@lab.ntt.co.jp&gt;
Acked-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: remove homegrown L1_CACHE_ALIGN macro</title>
<updated>2010-07-06T17:41:57Z</updated>
<author>
<name>FUJITA Tomonori</name>
<email>fujita.tomonori@lab.ntt.co.jp</email>
</author>
<published>2010-06-29T07:32:42Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f'/>
<id>urn:sha1:4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f</id>
<content type='text'>
Let's use the standard L1_CACHE_ALIGN macro instead.

Signed-off-by: FUJITA Tomonori &lt;fujita.tomonori@lab.ntt.co.jp&gt;
Acked-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: core support for Tilera 32-bit chips.</title>
<updated>2010-06-04T21:11:18Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-05-29T03:09:12Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/linux/commit/?id=867e359b97c970a60626d5d76bbe2a8fadbf38fb'/>
<id>urn:sha1:867e359b97c970a60626d5d76bbe2a8fadbf38fb</id>
<content type='text'>
This change is the core kernel support for TILEPro and TILE64 chips.
No driver support (except the console driver) is included yet.

This includes the relevant Linux headers in asm/; the low-level
low-level "Tile architecture" headers in arch/, which are
shared with the hypervisor, etc., and are build-system agnostic;
and the relevant hypervisor headers in hv/.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: FUJITA Tomonori &lt;fujita.tomonori@lab.ntt.co.jp&gt;
Reviewed-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
</feed>
