linux/arch/mips/kernel/Makefile, branch mybooklive-amatus

MIPS: OCTEON: Enable use of FPU

2014-05-30T19:01:09Z

Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: David Daney Signed-off-by: Andreas Herrmann Cc: linux-mips@linux-mips.org Cc: James Hogan Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/ Signed-off-by: Ralf Baechle

Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into mips-for-linux-next

2014-05-29T13:08:23Z

MIPS: pm-cps: add PM state entry code for CPS systems

2014-05-28T15:20:31Z

This patch adds code to generate entry & exit code for various low power states available on systems based around the MIPS Coherent Processing System architecture (ie. those with a Coherence Manager, Global Interrupt Controller & for >=CM2 a Cluster Power Controller). States supported are: - Non-coherent wait. This state first leaves the coherent domain and then executes a regular MIPS wait instruction. Power savings are found from the elimination of coherency interventions between the core and any other coherent requestors in the system. - Clock gated. This state leaves the coherent domain and then gates the clock input to the core. This removes all dynamic power from the core but leaves the core at the mercy of another to restart its clock. Register state is preserved, but the core can not service interrupts whilst its clock is gated. - Power gated. This deepest state removes all power input to the core. All register state is lost and the core will restart execution from its BEV when another core powers it back up. Because register state is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP implementation in order for the core to exit the state successfully. The code will detect which states are available on the current system during boot & generate the entry/exit code for those states. This will be used by cpuidle & hotplug implementations. Signed-off-by: Paul Burton

MIPS: MT: Remove SMTC support

2014-05-23T22:07:01Z

Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle

MIPS: PM: Add CPU PM callbacks for general CPU context

2014-04-24T14:15:54Z

Add a CPU power management notifier callback for preserving general CPU context. The CPU PM callbacks will be triggered by the powering down of CPU cores, for example by cpuidle drivers & in the future by suspend to RAM implementations. The current state preserved is mostly related to the process context: - FPU - DSP - ASID - UserLocal - Watch registers Signed-off-by: James Hogan Signed-off-by: Paul Burton

MIPS: Coherent Processing System SMP implementation

2014-03-26T22:00:12Z

This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle

MIPS: Add CPC probe, access functions

2014-03-06T20:25:23Z

This patch introduces code to probe for a MIPS Cluster Power Controller & accessor functions to allow for easy register access. This support code will be used by a subsequent patch. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6361/ Signed-off-by: Ralf Baechle

MIPS: Add generic CM probe & access code

2014-03-06T20:25:22Z

The kernel currently only probes for a MIPS Coherence Manager in the Malta interrupt code in order to detect & enable the GIC. However CM is not Malta-specific, so this should really be more generic. This patch introduces some non-Malta-specific code which probes for a CM and performs some basic initialisation. A new header, with temporarily duplicated register definitions, is introduced in order to: 1) Allow the new definitions to be correct with regards to the CM documentation, as many of those in gcmpregs.h aren't. 2) Allow switching away from the REG() macro used via a few layers of nested macros in order to access registers in gcmpregs.h. This patch instead introduced accessor functions akin to the {read,write}_c0_* functions used for cop0 registers. 3) Allow users of the CM to be migrated one by one. 4) Switch from the name 'GCMP' to 'CM' since the Coherence Manager is what this code is actually dealing with. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6360/ Signed-off-by: Ralf Baechle

MIPS: Move GIC IPI functions out of smp-cmp.c

2014-03-06T20:25:22Z

The GIC IPI functions aren't necessarily specific to the "CMP framework" SMP implementation, and will be used elsewhere in a subsequent commit. This patch adds cleaned up GIC IPI functions to a separate file which is compiled when a new CONFIG_MIPS_GIC_IPI Kconfig symbol is selected, and selects that symbol for CONFIG_MIPS_CMP. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6359/ Signed-off-by: Ralf Baechle

MIPS: APRP: Add RTLX API support for CMP platforms.

2014-01-22T19:19:02Z

This patch adds RTLX API support for platforms having a CMP. Signed-off-by: Deng-Cheng Zhu Signed-off-by: Steven J. Hill Reviewed-by: Qais Yousef Patchwork: http://patchwork.linux-mips.org/patch/6095/ Reviewed-by: John Crispin