linux/arch/microblaze/kernel/head.S, branch v3.4.84

microblaze: Handle TLB skip size dynamically

2012-03-23T08:28:19Z

This patch fix the problem with rootfs on JFFS2 with early printk console turned on. The origin version used TLB63 for temporary early printk mapping. The code expect that kernel is not able to use all 64 TLB entries till early printk console is remapped by ioremap. After that temporary mapping on TLB63 is silently lost. This expectation give the opportunity to have early console pretty early. Microblaze systems with JFFS2 rootfs with early printk console turned on used more than 64 TLB entries before kernel can remap early console. Based on that kernel does access to bad area because early printk mapping is rewritten. This patch introduces tlb_skip variable which dynamically stores number of skipped TLB entries from the TLB0. skip_tlb=2 means that TLB0 and TLB1 should be skipped. MICROBLAZE_TLB_SKIP defines how many TLB is skipped at the kernel start. They can be used for user purpose. TLB 63 is used for temporary LMB mapping (MICROBLAZE_LMB_TLB_ID). Also clean TLBLO when kernel starts. For specific kernel sizes kernel can use just one TLB. Detect this case and use the second TLB for general purpose. Change _tlbia function to flush TLB entries from tlb_skip to TLB_SIZE. Export tlb_skip size through debugfs. Signed-off-by: Michal Simek

microblaze: Improve TLB calculation for small systems

2012-03-23T08:28:18Z

Systems with small amount of memory need to be handled differently. Linux can't allocate the whole 32MB with two TLBs because then there is no MMU protection. Signed-off-by: Michal Simek

microblaze: Extend space for compiled-in FDT to 32kB

2012-03-23T08:28:17Z

Signed-off-by: Michal Simek

microblaze: Clear all MSR flags on the first kernel instruction

2012-03-23T08:28:16Z

The main reason is bug because of dynamic TLB allocation. U-BOOT didn't disable dcache and then writing to physical address from ASM wan't visible for reading through MMU. Disabling caches and clearing all flags from previous code is good to do so. Signed-off-by: Michal Simek

microblaze: Do not use "la" pseudo instruction - use addik instead

2011-03-09T07:09:54Z

"la" pseudo instruction is only translation to "addik". Use directly "addik" which is described in the MB reference guide. Signed-off-by: Michal Simek

microblaze: Optimize BE/LE bootup detecting

2011-03-09T07:09:53Z

Save 0x1 word to rodata section and remove online value loading if DTB is passed from bootloader. It saves two asm instructions in bootup. Signed-off-by: Michal Simek

microblaze: Fix msr instruction detection

2011-02-07T18:13:01Z

Fix msr instructions detection. The current code just use msrclr for loading msr content and compare it with proper MSR content. If msrclr is not implemented r8 contains pc address. Previous code wanted to use MSR carry bit but if msrclr wasn't implemented carry wasn't cleared. Signed-off-by: Michal Simek

microblaze: Fix DTB passing from bootloader

2011-01-28T13:04:36Z

Little endian system needs to check OF_DT_HEADER but it is swapped because it is in big-endian. Microblaze LE provides lwr instruction which loads magic number in BIG endian format which can be compared. There is used the fact that if you write 0x1 as word and load it as byte then you get for big-endian zero and 1 for little-endian. Signed-off-by: Michal Simek

microblaze: Allow PAGE_SIZE configuration

2010-08-04T08:22:34Z

Allow developer to configure memory page size at compile time. Larger pages can improve performance on some workloads. Based on PowerPC code. Signed-off-by: Steven J. Magnani Signed-off-by: Michal Simek

microblaze: Quiet section mismatch warnings

2010-05-06T09:21:57Z

_start is located in .text, which causes mismatch warnings with machine_early_init() and start_kernel() in .init.text. Signed-off-by: Steven J. Magnani Signed-off-by: Michal Simek