linux/arch/microblaze/kernel/head.S, branch v3.2.51

microblaze: Do not use "la" pseudo instruction - use addik instead

2011-03-09T07:09:54Z

"la" pseudo instruction is only translation to "addik". Use directly "addik" which is described in the MB reference guide. Signed-off-by: Michal Simek

microblaze: Optimize BE/LE bootup detecting

2011-03-09T07:09:53Z

Save 0x1 word to rodata section and remove online value loading if DTB is passed from bootloader. It saves two asm instructions in bootup. Signed-off-by: Michal Simek

microblaze: Fix msr instruction detection

2011-02-07T18:13:01Z

Fix msr instructions detection. The current code just use msrclr for loading msr content and compare it with proper MSR content. If msrclr is not implemented r8 contains pc address. Previous code wanted to use MSR carry bit but if msrclr wasn't implemented carry wasn't cleared. Signed-off-by: Michal Simek

microblaze: Fix DTB passing from bootloader

2011-01-28T13:04:36Z

Little endian system needs to check OF_DT_HEADER but it is swapped because it is in big-endian. Microblaze LE provides lwr instruction which loads magic number in BIG endian format which can be compared. There is used the fact that if you write 0x1 as word and load it as byte then you get for big-endian zero and 1 for little-endian. Signed-off-by: Michal Simek

microblaze: Allow PAGE_SIZE configuration

2010-08-04T08:22:34Z

Allow developer to configure memory page size at compile time. Larger pages can improve performance on some workloads. Based on PowerPC code. Signed-off-by: Steven J. Magnani Signed-off-by: Michal Simek

microblaze: Quiet section mismatch warnings

2010-05-06T09:21:57Z

_start is located in .text, which causes mismatch warnings with machine_early_init() and start_kernel() in .init.text. Signed-off-by: Steven J. Magnani Signed-off-by: Michal Simek

microblaze: head.S typo fix

2010-04-01T06:38:24Z

I forget to change register name in comments. Signed-off-by: Michal Simek

microblaze: Use MICROBLAZE_TLB_SIZE in asm code

2010-04-01T06:38:24Z

TLB size was hardcoded in asm code. This patch brings ability to change TLB size only in one place. (mmu.h). Signed-off-by: Michal Simek

microblaze: Support systems without lmb bram

2010-04-01T06:38:23Z

When the system has no lmb bram, main memory should be start from zero because of microblaze vectors. DTS fragment could look like: DDR2_SDRAM: memory@0 { device_type = "memory"; reg = < 0x0 0x10000000 >; } ; Then you have to setup CONFIG_KERNEL_BASE_ADDR=0 which caused that kernel physical start address will be zero. On reset vector place will be jump to 0x100 and on 0x100 starts kernel text. You have to solve how to load the kernel before cpu starts. Tested with XMD. Signed-off-by: Michal Simek

microblaze: Change temp register for cmdline

2010-03-11T13:08:55Z

For copy was used r7 register when CONFIG_CMDLINE_BOOL option is enabled. But r7 stores pointer to fdt that's why machine_early_init not detect compiled-in DTB. I also moved kernel PID setup to have TLB init in one block Signed-off-by: Michal Simek