linux/arch/microblaze/kernel/cpu, branch v2.6.38Linux kernel source treehttps://git.amat.us/linux/atom/arch/microblaze/kernel/cpu?h=v2.6.382011-02-07T18:12:17Zmicroblaze: Fix asm compilation warning2011-02-07T18:12:17ZMichal Simekmonstr@monstr.eu2011-02-07T10:29:43Zurn:sha1:1649700408531ec64ae33af55a1091db50d1f7da
Microblaze ASM doesn't support hex values for mfs instructions.
/tmp/ccwiXVmt.s: Assembler messages:
/tmp/ccwiXVmt.s:19: Warning: ignoring operands: x00
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Add PVR for Microblaze v8.00.b2011-01-03T09:08:16ZMichal Simekmonstr@monstr.eu2010-12-28T13:44:51Zurn:sha1:a3c26959cc893cafc78a8c4e7d7ca6d4ffe4525c
Microblaze v8.00.b have 0x13 version string.
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Add PVR for endians plus detection2010-10-21T05:51:57ZMichal Simekmonstr@monstr.eu2010-08-13T10:47:42Zurn:sha1:8e2ad016b20f98790d5995aae1d157d1613ab9e6
Upcomming microblaze version will support little-endian.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
microblaze: Remove hardcoded asm instraction for PVR loading2010-10-21T05:51:46ZMichal Simekmonstr@monstr.eu2010-09-28T05:43:59Zurn:sha1:a7d8355008e4f6bbdcb8f998328afa685cec959c
It comes from past where pvr wasn't supported in msr instruction.
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Add new microblaze versions2010-10-21T05:51:35ZMichal Simekmonstr@monstr.eu2010-08-13T10:44:17Zurn:sha1:f66efecad0b468214f574b295f4152aa95d74d4e
PVR for 7.30.b, 8.00.a versions.
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Allow PAGE_SIZE configuration2010-08-04T08:22:34ZSteven J. Magnanisteve@digidescorp.com2010-05-13T15:48:27Zurn:sha1:ba9c4f88d747836bf35c3eee36aa18d2e164f493
Allow developer to configure memory page size at compile time.
Larger pages can improve performance on some workloads.
Based on PowerPC code.
Signed-off-by: Steven J. Magnani <steve@digidescorp.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Remove compilation warnings in cache macro2010-05-13T08:55:47ZMichal Simekmonstr@monstr.eu2010-05-13T08:55:47Zurn:sha1:ddfbc935eae68294834dc29998f93147a5422a0d
CC arch/microblaze/kernel/cpu/cache.o
arch/microblaze/kernel/cpu/cache.c: In function '__invalidate_dcache_range_wb':
arch/microblaze/kernel/cpu/cache.c:398: warning: ISO C90 forbids mixed declarations and code
arch/microblaze/kernel/cpu/cache.c: In function '__flush_dcache_range_wb':
arch/microblaze/kernel/cpu/cache.c:509: warning: ISO C90 forbids mixed declara
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros2010-05-06T09:22:00ZMichal Simekmonstr@monstr.eu2010-04-26T06:54:13Zurn:sha1:3274c5707c22221574b396d140d0db3480a2027a
1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CACHE_LOOP_LIMITS.
C implementation do not need aligned end address and ASM code do aligned
in their macros
4. ASM optimized CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
Because end address is compound from start + size, end address is the first address
which is exclude.
Here is the corresponding code which describe it.
+ int align = ~(line_length - 1);
+ end = ((end & align) == end) ? end - line_length : end & align;
a) end is aligned:
it is necessary to subtruct line length because we don't want to work with
next cacheline
b) end address is not aligned:
Just align it to be ready for ASM code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: cpuinfo shows cache line length2010-05-06T09:21:59ZMichal Simekmonstr@monstr.eu2010-04-26T11:53:04Zurn:sha1:77543cebab7387eab7d482e90018a64d6f2ced1e
Show cache line length in /proc/cpuinfo.
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Fix typo fault in cache code2010-05-06T09:21:59ZMichal Simekmonstr@monstr.eu2010-04-23T09:38:43Zurn:sha1:c17e1a1cedb723d48d4822cae1af1c010b608b5c
Copy & paste error.
Signed-off-by: Michal Simek <monstr@monstr.eu>