linux/arch/microblaze/kernel/cpu/cache.c, branch v3.4.84

Fix common misspellings

2011-03-31T14:26:23Z

Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi

microblaze: Fix sparse warnings - cache.c

2011-03-09T07:09:58Z

Warning log: CHECK arch/microblaze/kernel/cpu/cache.c arch/microblaze/kernel/cpu/cache.c:522:21: warning: symbol 'wb_msr' was not declared. Should it be static? arch/microblaze/kernel/cpu/cache.c:538:21: warning: symbol 'wb_nomsr' was not declared. Should it be static? arch/microblaze/kernel/cpu/cache.c:554:21: warning: symbol 'wt_msr' was not declared. Should it be static? arch/microblaze/kernel/cpu/cache.c:569:21: warning: symbol 'wt_nomsr' was not declared. Should it be static? arch/microblaze/kernel/cpu/cache.c:585:21: warning: symbol 'wt_msr_noirq' was not declared. Should it be static? arch/microblaze/kernel/cpu/cache.c:600:21: warning: symbol 'wt_nomsr_noirq' was not declared. Should it be static? Signed-off-by: Michal Simek

microblaze: Label MB 7.20.d as broken with WB cache

2011-03-09T07:09:55Z

MB version 7.20.d contains fault which is related with WB that's why error message will be shown. Signed-off-by: Michal Simek

microblaze: Remove compilation warnings in cache macro

2010-05-13T08:55:47Z

CC arch/microblaze/kernel/cpu/cache.o arch/microblaze/kernel/cpu/cache.c: In function '__invalidate_dcache_range_wb': arch/microblaze/kernel/cpu/cache.c:398: warning: ISO C90 forbids mixed declarations and code arch/microblaze/kernel/cpu/cache.c: In function '__flush_dcache_range_wb': arch/microblaze/kernel/cpu/cache.c:509: warning: ISO C90 forbids mixed declara Signed-off-by: Michal Simek

microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros

2010-05-06T09:22:00Z

1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP 2. Change BUG_ON to WARN_ON 3. Remove end aligned from CACHE_LOOP_LIMITS. C implementation do not need aligned end address and ASM code do aligned in their macros 4. ASM optimized CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address. Because end address is compound from start + size, end address is the first address which is exclude. Here is the corresponding code which describe it. + int align = ~(line_length - 1); + end = ((end & align) == end) ? end - line_length : end & align; a) end is aligned: it is necessary to subtruct line length because we don't want to work with next cacheline b) end address is not aligned: Just align it to be ready for ASM code. Signed-off-by: Michal Simek

microblaze: Fix typo fault in cache code

2010-05-06T09:21:59Z

Copy & paste error. Signed-off-by: Michal Simek

microblaze: Add define for ASM_LOOP

2010-03-11T13:12:50Z

It is default option but both options must be measured. Signed-off-by: Michal Simek

microblaze: remove trailing space in messages

2010-03-11T13:09:29Z

Signed-off-by: Frans Pop Cc: microblaze-uclinux@itee.uq.edu.au Cc: Michal Simek Signed-off-by: Michal Simek

microblaze: Move cache function to cache.c

2010-03-11T13:07:57Z

It is better to have init cache handling on one place. Signed-off-by: Michal Simek

microblaze: Fix cache loop function for cache range

2010-02-24T12:18:29Z

I create wrong asm code but none test shows that this part of code is wrong. I am not convinces that were good idea to create asm optimized macros for caches. The reason is that there is not optimization with previous code that's why make sense to add old code and do some benchmarking which functions are faster. Signed-off-by: Michal Simek