linux/arch/microblaze/include/asm/cache.h, branch v3.0.43Linux kernel source treehttps://git.amat.us/linux/atom/arch/microblaze/include/asm/cache.h?h=v3.0.432010-05-06T09:21:59Zmicroblaze: Define correct L1_CACHE_SHIFT value2010-05-06T09:21:59ZMichal Simekmonstr@monstr.eu2010-04-26T11:43:23Zurn:sha1:598acab44dcbda0e300d9d080e81566334138e7d
Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.
We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.
Here is the calculation for cacheline lenght 8 32bit=4Byte values
which is corresponding with SHIFT 5.
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Move cache macro from cache.h to cacheflush.h2009-12-14T07:45:00ZMichal Simekmonstr@monstr.eu2009-10-15T13:18:13Zurn:sha1:a1f55113ca2130f775eeebe799a401619bfd0295
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze: Remove uncache shadow condition2009-04-23T14:09:16ZMichal Simekmonstr@monstr.eu2009-04-16T08:46:37Zurn:sha1:ceb8944b3a3dd3ec4094a476a44802cc32c4fc02
Uncached shadow feature is not supported in current
kernel code that's why I removed it.
Signed-off-by: Michal Simek <monstr@monstr.eu>
microblaze_v8: cache support2009-03-27T13:25:16ZMichal Simekmonstr@monstr.eu2009-03-27T13:25:16Zurn:sha1:8beb8503bfa305cd7d9efa590517a9c01e2f97b4
Reviewed-by: Ingo Molnar <mingo@elte.hu>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: John Linn <john.linn@xilinx.com>
Acked-by: John Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>