linux/arch/arm/kernel/arch_timer.c, branch v3.5.4Linux kernel source treehttps://git.amat.us/linux/atom/arch/arm/kernel/arch_timer.c?h=v3.5.42012-04-27T12:39:25ZARM: architected timers: remove support for non DT platforms2012-04-27T12:39:25ZMarc Zyngiermarc.zyngier@arm.com2012-04-27T12:18:42Zurn:sha1:fb8a99f9f6bdc908cbbd2284cee80c709d9f7c03
All mainline platforms using the ARM architected timers are DT
only. As such, remove the ad-hoc support that is not longer needed
anymore.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: architected timers: add support for UP timer2012-04-27T12:35:34ZMarc Zyngiermarc.zyngier@arm.com2012-01-20T10:47:00Zurn:sha1:273d16adbccdfe3e4a9d02d286b8f1d76dc9e63f
If CONFIG_LOCAL_TIMERS is not defined, let the architected timer
driver register a single clock_event_device that is used as a
global timer.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: architected timers: add DT support2012-04-27T12:35:34ZMarc Zyngiermarc.zyngier@arm.com2012-01-19T13:53:50Zurn:sha1:0075242b3a2f78901172aaadf73beed762a1f02f
Add runtime DT support and documentation for the Cortex A7/A15
architected timers.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: architected timers: Add A15 specific sched_clock implementation2012-04-27T12:35:33ZMarc Zyngiermarc.zyngier@arm.com2011-01-14T15:32:36Zurn:sha1:3f61c80eb7dff0fb35beb8068852d3fc902315a6
Provide an A15 sched_clock implementation using the virtual counter,
which is thought to be more useful than the physical one in a
virtualised environment, as it can offset the time spent in another
VM or the hypervisor.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: local timers: Add A15 architected timer support2012-04-27T12:35:33ZMarc Zyngiermarc.zyngier@arm.com2012-01-11T17:25:17Zurn:sha1:022c03a2d650c641fa0f94dbc9d9ff77f8057678
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>