From a809c8db3d052e9b7dfaf8665ab3ce1a0b0dc859 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Tue, 23 Apr 2013 23:45:16 +0000 Subject: Machine model: Generate table entries for super-resources. Super-resources and resource groups are two ways of expressing overlapping sets of processor resources. Now we generate table entries the same way for both so the scheduler never needs to explicitly check for super-resources. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180162 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/SubtargetEmitter.cpp | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) (limited to 'utils/TableGen') diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 0d36c4fd46..4918b1b143 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -782,29 +782,38 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, } // Expand an explicit list of processor resources into a full list of implied -// resource groups that cover them. -// -// FIXME: Effectively consider a super-resource a group that include all of its -// subresources to allow mixing and matching super-resources and groups. -// -// FIXME: Warn if two overlapping groups don't have a common supergroup. +// resource groups and super resources that cover them. void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, std::vector &Cycles, - const CodeGenProcModel &ProcModel) { + const CodeGenProcModel &PM) { // Default to 1 resource cycle. Cycles.resize(PRVec.size(), 1); for (unsigned i = 0, e = PRVec.size(); i != e; ++i) { + Record *PRDef = PRVec[i]; RecVec SubResources; - if (PRVec[i]->isSubClassOf("ProcResGroup")) { - SubResources = PRVec[i]->getValueAsListOfDefs("Resources"); - } + if (PRDef->isSubClassOf("ProcResGroup")) + SubResources = PRDef->getValueAsListOfDefs("Resources"); else { - SubResources.push_back(PRVec[i]); + SubResources.push_back(PRDef); + PRDef = SchedModels.findProcResUnits(PRVec[i], PM); + for (Record *SubDef = PRDef; + SubDef->getValueInit("Super")->isComplete();) { + if (SubDef->isSubClassOf("ProcResGroup")) { + // Disallow this for simplicitly. + PrintFatalError(SubDef->getLoc(), "Processor resource group " + " cannot be a super resources."); + } + Record *SuperDef = + SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM); + PRVec.push_back(SuperDef); + Cycles.push_back(Cycles[i]); + SubDef = SuperDef; + } } - for (RecIter PRI = ProcModel.ProcResourceDefs.begin(), - PRE = ProcModel.ProcResourceDefs.end(); + for (RecIter PRI = PM.ProcResourceDefs.begin(), + PRE = PM.ProcResourceDefs.end(); PRI != PRE; ++PRI) { - if (*PRI == PRVec[i] || !(*PRI)->isSubClassOf("ProcResGroup")) + if (*PRI == PRDef || !(*PRI)->isSubClassOf("ProcResGroup")) continue; RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources"); RecIter SubI = SubResources.begin(), SubE = SubResources.end(); -- cgit v1.2.3-18-g5258