From c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 29 Mar 2012 18:03:59 +0000 Subject: Add more constness to CodeGenRegisters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/CodeGenRegisters.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'utils/TableGen/CodeGenRegisters.cpp') diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 9c61f3f7df..d86ca7a282 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -231,7 +231,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) { } void -CodeGenRegister::addSubRegsPreOrder(SetVector &OSet, +CodeGenRegister::addSubRegsPreOrder(SetVector &OSet, CodeGenRegBank &RegBank) const { assert(SubRegsComplete && "Must precompute sub-registers"); std::vector Indices = TheDef->getValueAsListOfDefs("SubRegIndices"); @@ -1095,7 +1095,7 @@ CodeGenRegBank::getRegClassForRegister(Record *R) { } BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef Regs) { - SetVector Set; + SetVector Set; // First add Regs with all sub-registers. for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -1110,7 +1110,7 @@ BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef Regs) { for (unsigned i = 0; i != Set.size(); ++i) { const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); for (unsigned j = 0, e = SR.size(); j != e; ++j) { - CodeGenRegister *Super = SR[j]; + const CodeGenRegister *Super = SR[j]; if (!Super->CoveredBySubRegs || Set.count(Super)) continue; // This new super-register is covered by its sub-registers. -- cgit v1.2.3-70-g09d2