From edcbada3d06c5cf57d2dfd737eb925872bc6182b Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 6 Jul 2009 22:05:45 +0000 Subject: Added ARM::mls for armv6t2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74866 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/mls.ll | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 test/CodeGen/ARM/mls.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/ARM/mls.ll b/test/CodeGen/ARM/mls.ll new file mode 100644 index 0000000000..fd3a7b626b --- /dev/null +++ b/test/CodeGen/ARM/mls.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+v6t2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 + +define i32 @f1(i32 %a, i32 %b, i32 %c) { + %tmp1 = mul i32 %a, %b + %tmp2 = sub i32 %c, %tmp1 + ret i32 %tmp2 +} + +; sub doesn't commute, so no mls for this one +define i32 @f2(i32 %a, i32 %b, i32 %c) { + %tmp1 = mul i32 %a, %b + %tmp2 = sub i32 %tmp1, %c + ret i32 %tmp2 +} -- cgit v1.2.3-70-g09d2