From ebc64cf780e6e0200cd462f26e9925dcc7632f2b Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Wed, 10 Mar 2010 11:41:08 +0000 Subject: Lower add (mul a, b), c into MACCU / MACCS nodes which translate directly to the maccu / maccs instructions. We handle this in ExpandADDSUB since after type legalisation it is messy to recognise these operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98150 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/XCore/addsub64.ll | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'test/CodeGen') diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll index 70536644c3..0432e5e712 100644 --- a/test/CodeGen/XCore/addsub64.ll +++ b/test/CodeGen/XCore/addsub64.ll @@ -18,3 +18,27 @@ define i64 @sub64(i64 %a, i64 %b) { ; CHECK-NEXT: lsub r2, r0, r0, r2, r11 ; CHECK-NEXT: lsub r2, r1, r1, r3, r2 ; CHECK-NEXT: retsp 0 + +define i64 @maccu(i64 %a, i32 %b, i32 %c) { +entry: + %0 = zext i32 %b to i64 + %1 = zext i32 %c to i64 + %2 = mul i64 %1, %0 + %3 = add i64 %2, %a + ret i64 %3 +} +; CHECK: maccu: +; CHECK: maccu r1, r0, r3, r2 +; CHECK-NEXT: retsp 0 + +define i64 @maccs(i64 %a, i32 %b, i32 %c) { +entry: + %0 = sext i32 %b to i64 + %1 = sext i32 %c to i64 + %2 = mul i64 %1, %0 + %3 = add i64 %2, %a + ret i64 %3 +} +; CHECK: maccs: +; CHECK: maccs r1, r0, r3, r2 +; CHECK-NEXT: retsp 0 -- cgit v1.2.3-70-g09d2