From 03be3622aae67aa095bc047bcac88cdebebaafd6 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 6 Mar 2012 23:33:32 +0000 Subject: Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/shifter_operand.ll | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'test/CodeGen') diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 521ffa1c9e..eb971ff72e 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -54,12 +54,16 @@ declare i8* @malloc(...) define fastcc void @test4(i16 %addr) nounwind { entry: ; A8: test4: -; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A8: str [[REG]], [r0] +; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A8: str [[REG]], [r0, r1, lsl #2] +; A8-NOT: str [[REG]], [r0] ; A9: test4: -; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! -; A9: str [[REG]], [r0] +; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] +; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! +; A9: str [[REG]], [r0, r1, lsl #2] +; A9-NOT: str [[REG]], [r0] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* %2 = sext i16 %addr to i32 -- cgit v1.2.3-70-g09d2