From d2ca8135496ff7945e8a708dccb26b482e563a63 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 9 Oct 2010 01:03:04 +0000 Subject: Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/reg_sequence.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'test/CodeGen/ARM/reg_sequence.ll') diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index b96762abe3..1a95897c26 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -46,8 +46,8 @@ entry: ; CHECK: t2: ; CHECK: vld1.16 ; CHECK-NOT: vmov -; CHECK: vld1.16 ; CHECK: vmul.i16 +; CHECK: vld1.16 ; CHECK: vmul.i16 ; CHECK-NOT: vmov ; CHECK: vst1.16 -- cgit v1.2.3-70-g09d2