From 940f83e772ca2007d62faffc83094bd7e8da6401 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Tue, 26 Aug 2008 18:03:31 +0000 Subject: Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaInstrInfo.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp') diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index ec8857fc7f..b566de4510 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -133,15 +133,15 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 2; } -void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); + // Not yet supported! + return false; } if (DestRC == Alpha::GPRCRegisterClass) { @@ -151,9 +151,11 @@ void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, } else if (DestRC == Alpha::F8RCRegisterClass) { BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); + // Attempt to copy register that is not GPR or FPR + return false; } + + return true; } void -- cgit v1.2.3-70-g09d2