From df97cc67a685b849f5b90bb1135fea87df4d32fd Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Wed, 21 Jun 2006 15:42:36 +0000 Subject: Add memory operand and int regs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28896 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelLowering.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'lib/Target/Alpha/AlphaISelLowering.cpp') diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index b18ee86557..3f21616778 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -591,6 +591,7 @@ AlphaTargetLowering::getConstraintType(char ConstraintLetter) const { switch (ConstraintLetter) { default: break; case 'f': + case 'r': return C_RegisterClass; } return TargetLowering::getConstraintType(ConstraintLetter); @@ -614,6 +615,19 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, Alpha::F24, Alpha::F25, Alpha::F26, Alpha::F27, Alpha::F28, Alpha::F29, Alpha::F30, Alpha::F31, 0); + case 'r': + return make_vector(Alpha::R0 , Alpha::R1 , Alpha::R2 , + Alpha::R3 , Alpha::R4 , Alpha::R5 , + Alpha::R6 , Alpha::R7 , Alpha::R8 , + Alpha::R9 , Alpha::R10, Alpha::R11, + Alpha::R12, Alpha::R13, Alpha::R14, + Alpha::R15, Alpha::R16, Alpha::R17, + Alpha::R18, Alpha::R19, Alpha::R20, + Alpha::R21, Alpha::R22, Alpha::R23, + Alpha::R24, Alpha::R25, Alpha::R26, + Alpha::R27, Alpha::R28, Alpha::R29, + Alpha::R30, Alpha::R31, 0); + } } -- cgit v1.2.3-70-g09d2