From 83e3f67fb68d497b600da83a62f000fcce7868a9 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 17 Aug 2011 17:44:15 +0000 Subject: Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 1231 ++++++++++++----------- 1 file changed, 649 insertions(+), 582 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index cb7a45a257..98cdc64746 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -24,188 +24,201 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +// Pull DecodeStatus and its enum values into the global namespace. +typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; +#define Success llvm::MCDisassembler::Success +#define Unpredictable llvm::MCDisassembler::SoftFail +#define Fail llvm::MCDisassembler::Fail + +// Helper macro to perform setwise reduction of the current running status +// and another status, and return if the new status is Fail. +#define CHECK(S,X) do { \ + S = (DecodeStatus) ((int)S & (X)); \ + if (S == Fail) return Fail; \ + } while(0) + // Forward declare these because the autogenerated code will reference them. // Definitions are further down. -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, unsigned Insn, uint64_t Adddress, const void *Decoder); -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, +static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, +static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder); -static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" @@ -230,15 +243,14 @@ EDInstInfo *ThumbDisassembler::getEDInfo() const { return instInfoARM; } - -bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address,raw_ostream &os) const { +DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + const MemoryObject &Region, + uint64_t Address,raw_ostream &os) const { uint8_t bytes[4]; // We want to read exactly 4 bytes of data. if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) - return false; + return Fail; // Encoded as a small-endian 32-bit word in the stream. uint32_t insn = (bytes[3] << 24) | @@ -247,10 +259,10 @@ bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, (bytes[0] << 0); // Calling the auto-generated decoder function. - bool result = decodeARMInstruction32(MI, insn, Address, this); - if (result) { + DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); + if (result != Fail) { Size = 4; - return true; + return result; } // Instructions that are shared between ARM and Thumb modes. @@ -258,53 +270,53 @@ bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, // fact that we fail to encode a few instructions properly for Thumb. MI.clear(); result = decodeCommonInstruction32(MI, insn, Address, this); - if (result) { + if (result != Fail) { Size = 4; - return true; + return result; } // VFP and NEON instructions, similarly, are shared between ARM // and Thumb modes. MI.clear(); result = decodeVFPInstruction32(MI, insn, Address, this); - if (result) { + if (result != Fail) { Size = 4; - return true; + return result; } MI.clear(); result = decodeNEONDataInstruction32(MI, insn, Address, this); - if (result) { + if (result != Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; - return true; + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; + return result; } MI.clear(); result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); - if (result) { + if (result != Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; - return true; + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; + return result; } MI.clear(); result = decodeNEONDupInstruction32(MI, insn, Address, this); - if (result) { + if (result != Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. - if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; - return true; + if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; + return result; } MI.clear(); - return false; + return Fail; } namespace llvm { @@ -403,22 +415,21 @@ void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { } } - -bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address,raw_ostream &os) const { +DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + const MemoryObject &Region, + uint64_t Address,raw_ostream &os) const { uint8_t bytes[4]; // We want to read exactly 2 bytes of data. if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) - return false; + return Fail; uint16_t insn16 = (bytes[1] << 8) | bytes[0]; - bool result = decodeThumbInstruction16(MI, insn16, Address, this); - if (result) { + DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); + if (result != Fail) { Size = 2; AddThumbPredicate(MI); - return true; + return result; } MI.clear(); @@ -428,12 +439,12 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, bool InITBlock = !ITBlock.empty(); AddThumbPredicate(MI); AddThumb1SBit(MI, InITBlock); - return true; + return result; } MI.clear(); result = decodeThumb2Instruction16(MI, insn16, Address, this); - if (result) { + if (result != Fail) { Size = 2; AddThumbPredicate(MI); @@ -456,12 +467,12 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ITBlock.push_back(firstcond); } - return true; + return result; } // We want to read exactly 4 bytes of data. if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) - return false; + return Fail; uint32_t insn32 = (bytes[3] << 8) | (bytes[2] << 0) | @@ -469,44 +480,44 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, (bytes[0] << 16); MI.clear(); result = decodeThumbInstruction32(MI, insn32, Address, this); - if (result) { + if (result != Fail) { Size = 4; bool InITBlock = ITBlock.size(); AddThumbPredicate(MI); AddThumb1SBit(MI, InITBlock); - return true; + return result; } MI.clear(); result = decodeThumb2Instruction32(MI, insn32, Address, this); - if (result) { + if (result != Fail) { Size = 4; AddThumbPredicate(MI); - return true; + return result; } MI.clear(); result = decodeCommonInstruction32(MI, insn32, Address, this); - if (result) { + if (result != Fail) { Size = 4; AddThumbPredicate(MI); - return true; + return result; } MI.clear(); result = decodeVFPInstruction32(MI, insn32, Address, this); - if (result) { + if (result != Fail) { Size = 4; UpdateThumbVFPPredicate(MI); - return true; + return result; } MI.clear(); result = decodeNEONDupInstruction32(MI, insn32, Address, this); - if (result) { + if (result != Fail) { Size = 4; AddThumbPredicate(MI); - return true; + return result; } if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { @@ -515,10 +526,10 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, NEONLdStInsn &= 0xF0FFFFFF; NEONLdStInsn |= 0x04000000; result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); - if (result) { + if (result != Fail) { Size = 4; AddThumbPredicate(MI); - return true; + return result; } } @@ -529,14 +540,14 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); - if (result) { + if (result != Fail) { Size = 4; AddThumbPredicate(MI); - return true; + return result; } } - return false; + return Fail; } @@ -554,30 +565,30 @@ static const unsigned GPRDecoderTable[] = { ARM::R12, ARM::SP, ARM::LR, ARM::PC }; -static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) - return false; + return Fail; unsigned Register = GPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return Success; } -static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo == 15) return false; + if (RegNo == 15) return Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } -static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) - return false; + return Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } -static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register = 0; switch (RegNo) { @@ -600,16 +611,16 @@ static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, Register = ARM::R12; break; default: - return false; + return Fail; } Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return Success; } -static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo == 13 || RegNo == 15) return false; + if (RegNo == 13 || RegNo == 15) return Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } @@ -624,14 +635,14 @@ static const unsigned SPRDecoderTable[] = { ARM::S28, ARM::S29, ARM::S30, ARM::S31 }; -static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) - return false; + return Fail; unsigned Register = SPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return Success; } static const unsigned DPRDecoderTable[] = { @@ -645,27 +656,27 @@ static const unsigned DPRDecoderTable[] = { ARM::D28, ARM::D29, ARM::D30, ARM::D31 }; -static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) - return false; + return Fail; unsigned Register = DPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return Success; } -static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) - return false; + return Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } -static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) - return false; + return Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } @@ -677,65 +688,66 @@ static const unsigned QPRDecoderTable[] = { }; -static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, +static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 31) - return false; + return Fail; RegNo >>= 1; unsigned Register = QPRDecoderTable[RegNo]; Inst.addOperand(MCOperand::CreateReg(Register)); - return true; + return Success; } -static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - if (Val == 0xF) return false; + if (Val == 0xF) return Fail; // AL predicate is not allowed on Thumb1 branches. if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) - return false; + return Fail; Inst.addOperand(MCOperand::CreateImm(Val)); if (Val == ARMCC::AL) { Inst.addOperand(MCOperand::CreateReg(0)); } else Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); - return true; + return Success; } -static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val) Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); else Inst.addOperand(MCOperand::CreateReg(0)); - return true; + return Success; } -static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { uint32_t imm = Val & 0xFF; uint32_t rot = (Val & 0xF00) >> 7; uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); Inst.addOperand(MCOperand::CreateImm(rot_imm)); - return true; + return Success; } -static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Val <<= 2; Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); - return true; + return Success; } -static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned type = fieldFromInstruction32(Val, 5, 2); unsigned imm = fieldFromInstruction32(Val, 7, 5); // Register-immediate - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); ARM_AM::ShiftOpc Shift = ARM_AM::lsl; switch (type) { @@ -759,19 +771,20 @@ static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, unsigned Op = Shift | (imm << 3); Inst.addOperand(MCOperand::CreateImm(Op)); - return true; + return S; } -static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned type = fieldFromInstruction32(Val, 5, 2); unsigned Rs = fieldFromInstruction32(Val, 8, 4); // Register-register - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; - if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); ARM_AM::ShiftOpc Shift = ARM_AM::lsl; switch (type) { @@ -791,49 +804,55 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, Inst.addOperand(MCOperand::CreateImm(Shift)); - return true; + return S; } -static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + // Empty register lists are not allowed. - if (CountPopulation_32(Val) == 0) return false; + if (CountPopulation_32(Val) == 0) return Fail; for (unsigned i = 0; i < 16; ++i) { if (Val & (1 << i)) { - if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); } } - return true; + return S; } -static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Vd = fieldFromInstruction32(Val, 8, 4); unsigned regs = Val & 0xFF; - if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; + CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); for (unsigned i = 0; i < (regs - 1); ++i) { - if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; + CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); } - return true; + return S; } -static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Vd = fieldFromInstruction32(Val, 8, 4); unsigned regs = (Val & 0xFF) / 2; - if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); for (unsigned i = 0; i < (regs - 1); ++i) { - if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); } - return true; + return S; } -static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { // This operand encodes a mask of contiguous zeros between a specified MSB // and LSB. To decode it, we create the mask of all bits MSB-and-lower, @@ -845,11 +864,13 @@ static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, uint32_t msb_mask = (1 << (msb+1)) - 1; uint32_t lsb_mask = (1 << lsb) - 1; Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); - return true; + return Success; } -static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); unsigned CRd = fieldFromInstruction32(Insn, 12, 4); unsigned coproc = fieldFromInstruction32(Insn, 8, 4); @@ -875,7 +896,7 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_POST: case ARM::STCL_OPTION: if (coproc == 0xA || coproc == 0xB) - return false; + return Fail; break; default: break; @@ -883,7 +904,7 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, Inst.addOperand(MCOperand::CreateImm(coproc)); Inst.addOperand(MCOperand::CreateImm(CRd)); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); switch (Inst.getOpcode()) { case ARM::LDC_OPTION: case ARM::LDCL_OPTION: @@ -952,17 +973,19 @@ static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STCL_PRE: case ARM::STCL_POST: case ARM::STCL_OPTION: - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); break; default: break; } - return true; + return S; } -static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rm = fieldFromInstruction32(Insn, 0, 4); @@ -982,13 +1005,13 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STRT_POST_IMM: case ARM::STRBT_POST_REG: case ARM::STRBT_POST_IMM: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); break; default: break; } - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); // On loads, the writeback operand comes after Rt. switch (Inst.getOpcode()) { @@ -1002,14 +1025,13 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRBT_POST_IMM: case ARM::LDRT_POST_REG: case ARM::LDRT_POST_IMM: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); break; default: break; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); ARM_AM::AddrOpc Op = ARM_AM::add; if (!fieldFromInstruction32(Insn, 23, 1)) @@ -1022,10 +1044,10 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, else if (!P && writeback) idx_mode = ARMII::IndexModePost; - if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE + if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE if (reg) { - if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); ARM_AM::ShiftOpc Opc = ARM_AM::lsl; switch( fieldFromInstruction32(Insn, 5, 2)) { case 0: @@ -1041,7 +1063,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, Opc = ARM_AM::ror; break; default: - return false; + return Fail; } unsigned amt = fieldFromInstruction32(Insn, 7, 5); unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); @@ -1053,13 +1075,15 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, Inst.addOperand(MCOperand::CreateImm(tmp)); } - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); - return true; + return S; } -static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rn = fieldFromInstruction32(Val, 13, 4); unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned type = fieldFromInstruction32(Val, 5, 2); @@ -1082,8 +1106,8 @@ static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, break; } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); unsigned shift; if (U) shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); @@ -1091,11 +1115,13 @@ static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); Inst.addOperand(MCOperand::CreateImm(shift)); - return true; + return S; } -static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned Rm = fieldFromInstruction32(Insn, 0, 4); @@ -1116,7 +1142,7 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST: - if (Rt & 0x1) return false; + if (Rt & 0x1) return Fail; break; default: break; @@ -1136,16 +1162,14 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STRH: case ARM::STRH_PRE: case ARM::STRH_POST: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); break; default: break; } } - if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); switch (Inst.getOpcode()) { case ARM::STRD: case ARM::STRD_PRE: @@ -1153,8 +1177,7 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST: - if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); break; default: break; @@ -1177,33 +1200,32 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRSB_POST: case ARM::LDRHTr: case ARM::LDRSBTr: - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); break; default: break; } } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); if (type) { Inst.addOperand(MCOperand::CreateReg(0)); Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); } else { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(U)); } - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); - return true; + return S; } -static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned mode = fieldFromInstruction32(Insn, 23, 2); @@ -1223,14 +1245,16 @@ static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, } Inst.addOperand(MCOperand::CreateImm(mode)); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); - return true; + return S; } -static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, +static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); unsigned pred = fieldFromInstruction32(Insn, 28, 4); unsigned reglist = fieldFromInstruction32(Insn, 0, 16); @@ -1265,16 +1289,15 @@ static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, return DecodeRFEInstruction(Inst, Insn, Address, Decoder); } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || - !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied - !DecodePredicateOperand(Inst, pred, Address, Decoder) || - !DecodeRegListOperand(Inst, reglist, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); + CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); - return true; + return S; } -static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned imod = fieldFromInstruction32(Insn, 18, 2); unsigned M = fieldFromInstruction32(Insn, 17, 1); @@ -1282,30 +1305,32 @@ static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned mode = fieldFromInstruction32(Insn, 0, 5); // imod == '01' --> UNPREDICTABLE - if (imod == 1) return false; + if (imod == 1) return Fail; if (M && mode && imod && iflags) { Inst.setOpcode(ARM::CPS3p); Inst.addOperand(MCOperand::CreateImm(imod)); Inst.addOperand(MCOperand::CreateImm(iflags)); Inst.addOperand(MCOperand::CreateImm(mode)); - return true; + return Success; } else if (!mode && !M) { Inst.setOpcode(ARM::CPS2p); Inst.addOperand(MCOperand::CreateImm(imod)); Inst.addOperand(MCOperand::CreateImm(iflags)); - return true; + return Success; } else if (!imod && !iflags && M) { Inst.setOpcode(ARM::CPS1p); Inst.addOperand(MCOperand::CreateImm(mode)); - return true; + return Success; } - return false; + return Fail; } -static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rd = fieldFromInstruction32(Insn, 16, 4); unsigned Rn = fieldFromInstruction32(Insn, 0, 4); unsigned Rm = fieldFromInstruction32(Insn, 8, 4); @@ -1315,57 +1340,60 @@ static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || - !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || - !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || - !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) - return false; + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); + CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); - return true; + return S; } -static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned add = fieldFromInstruction32(Val, 12, 1); unsigned imm = fieldFromInstruction32(Val, 0, 12); unsigned Rn = fieldFromInstruction32(Val, 13, 4); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); if (!add) imm *= -1; if (imm == 0 && !add) imm = INT32_MIN; Inst.addOperand(MCOperand::CreateImm(imm)); - return true; + return S; } -static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rn = fieldFromInstruction32(Val, 9, 4); unsigned U = fieldFromInstruction32(Val, 8, 1); unsigned imm = fieldFromInstruction32(Val, 0, 8); - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); if (U) Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); else Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); - return true; + return S; } -static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); } -static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned pred = fieldFromInstruction32(Insn, 28, 4); unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; @@ -1373,39 +1401,42 @@ static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, Inst.setOpcode(ARM::BLXi); imm |= fieldFromInstruction32(Insn, 24, 1) << 1; Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); - return true; + return S; } Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); - if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; + CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); - return true; + return S; } -static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::CreateImm(64 - Val)); - return true; + return Success; } -static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, +static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rm = fieldFromInstruction32(Val, 0, 4); unsigned align = fieldFromInstruction32(Val, 4, 2); - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); if (!align) Inst.addOperand(MCOperand::CreateImm(0)); else Inst.addOperand(MCOperand::CreateImm(4 << align)); - return true; + return S; } -static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned wb = fieldFromInstruction32(Insn, 16, 4); @@ -1414,7 +1445,7 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned Rm = fieldFromInstruction32(Insn, 0, 4); // First output register - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Second output register switch (Inst.getOpcode()) { @@ -1466,7 +1497,7 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); break; case ARM::VLD2b8: case ARM::VLD2b16: @@ -1486,7 +1517,7 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); default: break; } @@ -1527,7 +1558,7 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); break; case ARM::VLD3q8: case ARM::VLD3q16: @@ -1541,7 +1572,7 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); break; default: break; @@ -1569,7 +1600,7 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4d8_UPD: case ARM::VLD4d16_UPD: case ARM::VLD4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); break; case ARM::VLD4q8: case ARM::VLD4q16: @@ -1577,7 +1608,7 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); break; default: break; @@ -1622,28 +1653,29 @@ static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD4q8_UPD: case ARM::VLD4q16_UPD: case ARM::VLD4q32_UPD: - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); break; default: break; } // AddrMode6 Base (register+alignment) - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); // AddrMode6 Offset (register) if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); } - return true; + return S; } -static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned wb = fieldFromInstruction32(Insn, 16, 4); @@ -1690,25 +1722,24 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) - return false; + CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); break; default: break; } // AddrMode6 Base (register+alignment) - if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); // AddrMode6 Offset (register) if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); } // First input register - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Second input register switch (Inst.getOpcode()) { @@ -1760,7 +1791,7 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); break; case ARM::VST2b8: case ARM::VST2b16: @@ -1780,7 +1811,7 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); break; default: break; @@ -1822,7 +1853,7 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); break; case ARM::VST3q8: case ARM::VST3q16: @@ -1836,7 +1867,7 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); break; default: break; @@ -1864,7 +1895,7 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4d8_UPD: case ARM::VST4d16_UPD: case ARM::VST4d32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); break; case ARM::VST4q8: case ARM::VST4q16: @@ -1872,17 +1903,19 @@ static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VST4q8_UPD: case ARM::VST4q16_UPD: case ARM::VST4q32_UPD: - if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); break; default: break; } - return true; + return S; } -static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, +static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeStatus S = Success; + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; unsigned Rn = fieldFromInstruction32(Insn, 16, 4); @@ -1893,28 +1926,30 @@ static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, align *= (1 << size); - if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); if (regs == 2) { - if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; + CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); } if (Rm == 0xD) { - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); } - if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); Inst.addOperand(MCOperand::CreateImm(align)); if (Rm == 0xD) Inst.addOperand(MCOperand::CreateReg(0)); else if (Rm != 0xF) { - if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; + CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); } - return true; + return S; } -stati