From 71156a6e00d3dc4c531a421a76b3b6ee0ae7d0ab Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Thu, 11 Aug 2011 19:00:18 +0000 Subject: Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 8a85cfade1..85e48c7165 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -978,6 +978,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, else if (!P && writeback) idx_mode = ARMII::IndexModePost; + if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE + if (reg) { if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; ARM_AM::ShiftOpc Opc = ARM_AM::lsl; -- cgit v1.2.3-18-g5258