From 77521f5232e679aa3de10aaaed2464aa91d7ff55 Mon Sep 17 00:00:00 2001 From: David Goodwin Date: Wed, 8 Jul 2009 20:28:28 +0000 Subject: Generalize opcode selection in ARMBaseRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Target/ARM/ARMInstrInfo.cpp') diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 0aaa311c0c..ab0a39177a 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -73,6 +73,7 @@ getOpcode(ARMII::Op Op) const { case ARMII::BR_JTr: return ARM::BR_JTr; case ARMII::BR_JTm: return ARM::BR_JTm; case ARMII::BR_JTadd: return ARM::BR_JTadd; + case ARMII::BX_RET: return ARM::BX_RET; case ARMII::FCPYS: return ARM::FCPYS; case ARMII::FCPYD: return ARM::FCPYD; case ARMII::FLDD: return ARM::FLDD; @@ -120,7 +121,7 @@ reMaterialize(MachineBasicBlock &MBB, const MachineInstr *Orig) const { DebugLoc dl = Orig->getDebugLoc(); if (Orig->getOpcode() == ARM::MOVi2pieces) { - RI.emitLoadConstPool(MBB, I, this, dl, + RI.emitLoadConstPool(MBB, I, dl, DestReg, Orig->getOperand(1).getImm(), (ARMCC::CondCodes)Orig->getOperand(2).getImm(), -- cgit v1.2.3-70-g09d2